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| Features * High-performance and Low-power AVR(R) 8-bit RISC Architecture - 118 Powerful Instructions - Most Single Cycle Execution - 32 x 8 General Purpose Working Registers - Up to 8 MIPS Throughput at 8 MHz Data and Non-volatile Program Memory - 4K Bytes of In-System Programmable Flash Endurance 1,000 Write/Erase Cycles - 128 Bytes of SRAM - 256 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles - Programming Lock for Flash Program and EEPROM Data Security Peripheral Features - One 8-bit Timer/Counter with Separate Prescaler - Expanded 16-bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and 8-, 9-, or 10-bit PWM - On-chip Analog Comparator - Programmable Watchdog Timer with Separate On-chip Oscillator - Programmable UART - 6-channel, 10-bit ADC - Master/Slave SPI Serial Interface Special Microcontroller Features - Brown-out Reset Circuit - Enhanced Power-on Reset Circuit - Low-power Idle and Power-down Modes Power Consumption at 4 MHz, 3V, 25C - Active: 3.4 mA - Idle Mode: 1.4 mA - Power-down Mode: <1 A I/O and Packages - 20 Programmable I/O Lines - 28-lead PDIP and 32-lead TQFP Operating Voltage - 2.7V - 6.0V for the AT90LS4433 - 4.0V - 6.0V for the AT90S4433 Speed Grades - 0 - 4 MHz for the AT90LS4433 - 0 - 8 MHz for the AT90S4433 * * * 8-bit Microcontroller with 4K Bytes of In-System Programmable Flash AT90S4433 AT90LS4433 Not Recommend for New Designs. Use ATmega8. * * * * Rev. 1042H-AVR-04/03 1 Pin Configurations TQFP Top View PD2 (INT0) PD1 (TXD) PD0 (RXD) RESET PC5 (ADC5) PC4 (ADC4) PC3 (ADC3) PC2 (ADC2) 32 31 30 29 28 27 26 25 (INT1) PD3 (T0) PD4 NC VCC GND NC XTAL1 XTAL2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 PC1 (ADC1) PC0 (ADC0) NC AGND AREF NC AVCC PB5 (SCK) RESET (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (T0) PD4 VCC GND XTAL1 XTAL2 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP) PB0 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP) PB0 (OC1) PB1 (SS) PB2 (MOSI) PB3 (MISO) PB4 PDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC5 (ADC5) PC4 (ADC4) PC3 (ADC3) PC2 (ADC2) PC1 (ADC1) PC0 (ADC0) AGND AREF AVCC PB5 (SCK) PB4 (MISO) PB3 (MOSI) PB2 (SS) PB1 (OC1) 2 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Description The AT90S4433 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S4433 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The AT90S4433 provides the following features: 4K bytes of In-System Programmable Flash, 256 bytes of EEPROM, 128 bytes of SRAM, 20 general purpose I/O lines, 32 general purpose working registers, two flexible Timer/Counters with compare modes, internal and external interrupts, a programmable serial UART, 6-channel, 10-bit ADC, programmable Watchdog Timer with internal Oscillator, an SPI serial port and two software-selectable Power-saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The device is manufactured using Atmel's high-density non-volatile memory technology. The On-chip Flash Program memory can be re-programmed In-System through an SPI serial interface or by a conventional non-volatile memory programmer. By combining a RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S4433 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. The AT90S4433 AVR is supported with a full suite of program and system development tools including: C Compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators and evaluation kits. Table 1. Comparison Table Device AT90S4433 AT90LS4433 Flash 4K 4K EEPROM 256B 256B SRAM 128B 128B Voltage Range 4.0V - 6.0V 2.7V - 6.0V Frequency 0 - 8 MHz 0 - 4 MHz 3 1042H-AVR-04/03 Block Diagram Figure 1. The AT90S4433 Block Diagram PC0 - PC5 VCC PORTC DRIVERS GND DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC ANALOG MUX AGND AREF ADC XTAL1 INTERNAL OSCILLATOR OSCILLATOR PROGRAM COUNTER STACK POINTER WATCHDOG TIMER TIMING AND CONTROL XTAL2 RESET PROGRAM FLASH SRAM MCU CONTROL REGISTER INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z TIMER/ COUNTERS INSTRUCTION DECODER INTERRUPT UNIT CONTROL LINES ALU EEPROM STATUS REGISTER PROGRAMMING LOGIC SPI UART DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTD DATA DIR. REG. PORTD + ANALOG COMPARATOR PORTB DRIVERS PORTD DRIVERS PB0 - PB5 PD0 - PD7 4 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Pin Descriptions VCC GND Port B (PB5..PB0) Supply voltage. Ground. Port B is a 6-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. Port B also serves the functions of various special features of the AT90S4433 as listed on page 73. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C (PC5..PC0) Port C is a 6-bit bi-directional I/O port with internal pull-up resistors. The Port C output buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. Port C also serves as the analog inputs to the A/D Converter. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features of the AT90S4433 as listed on page 81. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. RESET Reset input. An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. Input to the inverting oscillator amplifier and input to the internal clock operating circuit Output from the inverting oscillator amplifier AVCC is the supply voltage for Port A and the A/D Converter. If the ADC is not used, this pin must be connected to VCC. If the ADC is used, this pin should be connected to VCC via a low-pass filter. See page 64 for details on operation of the ADC. AREF is the analog reference input for the A/D Converter. For ADC operations, a voltage in the range 2.0V to AVCC must be applied to this pin. If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to GND. XTAL1 XTAL2 AVCC AREF AGND 5 1042H-AVR-04/03 Clock Options Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier, which can be configured for use as an On-chip Oscillator, as shown in Figure 2 and Figure 3. Either a quartz crystal or a ceramic resonator may be used. If the Oscillator is to be used as a clock for an external device, the clock signal from XTAL2 may be routed to one HC buffer while reducing the load capacitor by 5 pF, as shown in Figure 3. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 4. Figure 2. Oscillator Connections External Clock Figure 3. Using MCU Oscillator as a Clock for an External Device XTAL1 XTAL2 REDUCE BY 5PF HC MAX 1 HC BUFFER Figure 4. External Clock Drive Configuration 6 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Architectural Overview The fast-access Register File concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing, enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look-up function. These added function registers are the 16-bit X-, Y-, and Z-register. The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 5 shows the AT90S4433 AVR RISC microcontroller architecture. In addition to the register operation, the conventional Memory Addressing modes can be used on the Register File as well. This is enabled by the fact that the Register File is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations. Figure 5. The AT90S4433 AVR RISC Architecture Data Bus 8-bit 2K X 16 Program Memory Program Counter Status and Control Interrupt Unit Instruction Register 32 x 8 General Purpose Registrers SPI Unit Serial UART Indirect Addressing Instruction Decoder Direct Addressing ALU 8-bit Timer/Counter Control Lines 16-bit Timer/Counter with PWM 128 x 8 Data SRAM Watchdog Timer 256 x 8 EEPROM 20 I/O Lines Analog to Digital Converter Analog Comparator 7 1042H-AVR-04/03 The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, A/D Converters and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, $20 - $5F. The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The Program memory is executed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Programmable Flash memory. With the relative jump and call instructions, the whole 2K word address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM and, consequently, the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 8-bit Stack Pointer (SP) is read/write accessible in the I/O space. The 128 bytes of data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. 8 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Figure 6. AT90S4433 Memory Maps Program Memory $000 Data Memory 32 Gen. Purpose $0000 Working Registers $001F $0020 64 I/O Registers Program Flash (2K x 16) $005F $0060 Internal SRAM (128 x 8) $00DF $7FF A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All the different interrupts have a separate Interrupt Vector in the Interrupt Vector table at the beginning of the Program memory. The different interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. 9 1042H-AVR-04/03 General Purpose Register File Figure 7 shows the structure of the 32 general purpose working registers in the CPU. Figure 7. AVR CPU General Purpose Working Registers 7 R0 R1 R2 ... R13 General Purpose Working Registers R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 $1A $1B $1C $1D $1E $1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte $0D $0E $0F $10 $11 0 Addr. $00 $01 $02 All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exceptions are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the Register File (R16..R31). The general SBC, SUB, CP, AND, and OR, and all other operations between two registers or on a single register apply to the entire Register File. As shown in Figure 7, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- ,and Z-registers can be set to index any register in the file. X-register, Y-register and Zregister The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as: Figure 8. X-, Y-, and Z-registers 15 X - register 7 R27 ($1B) 0 7 R26 ($1A) 0 0 15 Y - register 7 R29 ($1D) 0 7 R28 ($1C) 0 0 15 Z - register 7 R31 ($1F) 0 7 R30 ($1E) 0 0 10 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions). ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the Register File are executed. The ALU operations are divided into three main categories: arithmetic, logical, and bit functions. The AT90S4433 contains 4K bytes of On-chip, In-System Programmable Flash memory for program storage. Since all instructions are 16- or 32-bit words, the Flash is organized as 2K x 16. The Flash memory has an endurance of at least 1,000 write/erase cycles. The AT90S4433 Program Counter (PC) is 11 bits wide, thus addressing the 2,048 program memory addresses. See page 93 for a detailed description of Flash data downloading. See page 12 for the different program memory addressing modes. Figure 9. SRAM Organization Register File R0 R1 R2 Data Address Space $0000 $0001 $0002 In-System Programmable Flash Program Memory R29 R30 R31 I/O Registers $00 $01 $02 ... $001D $001E $001F $0020 $0021 $0022 ... $3D $3E $3F $005D $005E $005F Internal SRAM $0060 $0061 $00DE $00DF SRAM Data Memory Figure 9 shows how the AT90S4433 SRAM memory is organized. The lower 224 data memory locations address the Register File, the I/O memory and the internal data SRAM. The first 96 locations address the Register File and I/O memory, and the next 128 locations address the internal data SRAM. The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers. 11 1042H-AVR-04/03 The direct addressing reaches the entire data space. The Indirect with Displacement mode features 63 address locations reached from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented and incremented. The 32 general purpose working registers, 64 I/O Registers and the 128 bytes of internal data SRAM in the AT90S4433 are all accessible through all these addressing modes. See the next section for a detailed description of the different addressing modes. Program and Data Addressing Modes The AT90S4433 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the Flash Program memory, SRAM, Register File, and I/O data memory. This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. Figure 10. Direct Single Register Addressing Register Direct, Single Register Rd The operand is contained in register d (Rd). Register Direct, Two Registers Rd and Rr Figure 11. Direct Register Addressing, Two Registers Operands are contained in registers r (Rr) and d (Rd). The result is stored in register d (Rd). 12 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 I/O Direct Figure 12. I/O Direct Addressing Operand address is contained in six bits of the instruction word. n is the destination or source register address. Data Direct Figure 13. Direct Data Addressing Data Space 31 OP 16 LSBs 15 0 20 19 Rr/Rd 16 $0000 $00DF A 16-bit data address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. Data Indirect with Displacement Figure 14. Data Indirect with Displacement Data Space $0000 15 Y OR Z - REGISTER 0 15 OP 10 n 65 a 0 $00DF Operand address is the result of the Y- or Z-register contents added to the address contained in six bits of the instruction word. 13 1042H-AVR-04/03 Data Indirect Figure 15. Data Indirect Addressing Data Space $0000 15 X, Y, OR Z - REGISTER 0 $00DF Operand address is the contents of the X-, Y-, or the Z-register. Data Indirect with Predecrement Figure 16. Data Indirect Addressing with Pre-decrement Data Space $0000 15 X, Y, OR Z - REGISTER 0 -1 $00DF The X-, Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or the Z-register. Data Indirect with Postincrement Figure 17. Data Indirect Addressing with Post-increment Data Space $0000 15 X, Y, OR Z - REGISTER 0 1 $00DF The X-, Y-, or the Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or the Z-register prior to incrementing. 14 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Constant Addressing Using the LPM Instruction Figure 18. Code Memory Constant Addressing PROGRAM MEMORY $000 $7FF Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 2K), the LSB selects Low Byte if cleared (LSB = 0) or High Byte if set (LSB = 1). Indirect Program Addressing, IJMP and ICALL Figure 19. Indirect Program Memory Addressing PROGRAM MEMORY $000 $7FF Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). Relative Program Addressing, RJMP and RCALL Figure 20. Relative Program Memory Addressing PROGRAM MEMORY $000 +1 $7FF Program execution continues at address PC + k + 1. The relative address k is from -2048 to 2047. 15 1042H-AVR-04/03 EEPROM Data Memory The AT90S4433 contains 256 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles per location. The access between the EEPROM and the CPU is described on page 53, specifying the EEPROM Address Registers, the EEPROM Data Register and the EEPROM Control Register. For the SPI Data downloading, see page 93 for a detailed description. The EEPROM Data memory is In-System Programmable through the SPI port. Please refer to the "EEPROM Read/Write Access" section on page 45 for a thorough description of EEPROM access. Memory Access Times and Instruction Execution Timing This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock O, directly generated from the external clock crystal for the chip. No internal clock division is used. Figure 21 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks and functions per power unit. Figure 21. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 System Clock O 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 22 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destination register. Figure 22. Single Cycle ALU Operation T1 T2 T3 T4 System Clock O Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back The internal data SRAM access is performed in two System Clock cycles as described in Figure 23. 16 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Figure 23. On-chip Data SRAM Access Cycles T1 T2 T3 T4 System Clock O Address Data WR Data RD Prev. Address Address I/O Memory The I/O space definition of the AT90S4433 is shown in Table 2. Table 2. AT90S4433 I/O Space(1) I/O Address (SRAM Address) $3F ($5F) $3D ($5D) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $27 ($47) $26 ($46) $21 ($41) $1E ($3E) $1D ($3D) $1C ($3C) $18 ($38) Name SREG SP GIMSK GIFR TIMSK TIFR MCUCR MCUSR TCCR0 TCNT0 TCCR1A TCCR1B TCNT1H TCNT1L OCR1H OCR1L ICR1H ICR1L WDTCR EEAR EEDR EECR PORTB Function Status Register Stack Pointer General Interrupt MaSK Register General Interrupt Flag Register Timer/Counter Interrupt MaSK Register Timer/Counter Interrupt Flag Register MCU general Control Register MCU general Status Register Timer/Counter0 Control Register Timer/Counter0 (8-bit) Timer/Counter1 Control Register A Timer/Counter1 Control Register B Timer/Counter1 High Byte Timer/Counter1 Low Byte Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Low Byte Timer/Counter1 Input Capture Register High Byte Timer/Counter 1 Input Capture Register Low Byte Watchdog Timer Control Register EEPROM Address Register EEPROM Data Register EEPROM Control Register Data Register, Port B Read Write 17 1042H-AVR-04/03 Table 2. AT90S4433 I/O Space(1) (Continued) I/O Address (SRAM Address) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) Note: Name DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRR ACSR ADMUX ADCSR ADCH ADCL UBRRHI Function Data Direction Register, Port B Input Pins, Port B Data Register, Port C Data Direction Register, Port C Input Pins, Port C Data Register, Port D Data Direction Register, Port D Input Pins, Port D SPI I/O Data Register SPI Status Register SPI Control Register UART I/O Data Register UART Control and Status Register A UART Control and Status Register B UART Baud Rate Register Analog Comparator Control and Status Register ADC Multiplexer Select Register ADC Control and Status Register ADC Data Register High ADC Data Register Low UART Baud Rate Register High 1. Reserved and unused locations are not shown in the table. All AT90S4433 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range $00 $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers as SRAM, $20 must be added to this address. All I/O Register addresses throughout this document are shown with the SRAM address in parentheses. For compatibility with future devices, reserved bits should be written to zero when accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical "1" to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. The I/O and Peripherals Control Registers are explained in the following sections. 18 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Status Register - SREG The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as: Bit $3F ($5F) Read/Write Initial Value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG * Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred and is set by the RETI instruction to enable subsequent interrupts. * Bit 6 - T: Bit Copy Storage The Bit Copy Instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. * Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetical operations. See the Instruction Set description for detailed information. * Bit 4 - S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. See the Instruction Set description for detailed information. * Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetics. See the Instruction Set description for detailed information. * Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result from an arithmetical or logical operation. See the Instruction Set description for detailed information. * Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result from an arithmetical or logical operation. See the Instruction Set description for detailed information. * Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetical or logical operation. See the Instruction Set description for detailed information. Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. 19 1042H-AVR-04/03 Stack Pointer - SP The AT90S4433 Stack Pointer is implemented as an 8-bit register in the I/O space location $3D ($5D). As the AT90S4433 data memory has $0DF locations, eight bits are used. 7 $3D ($5D) Read/Write Initial Value SP7 R/W 0 6 SP6 R/W 0 5 SP5 R/W 0 4 SP4 R/W 0 3 SP3 R/W 0 2 SP2 R/W 0 1 SP1 R/W 0 0 SP0 R/W 0 SP The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt stacks are located. This stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt RETI. Reset and Interrupt Handling The AT90S4433 provides 13 different interrupt sources. These interrupts and the separate reset vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits, which must be set (one) together with the I-bit in the Status Register in order to enable the interrupt. The lowest addresses in the Program memory space are automatically defined as the Reset and Interrupt Vectors. The complete list of Vectors is shown in Table 3. The list also determines the priority levels of the different interrupts. The lower the address, the higher the priority level. RESET has the highest priority, and next is INT0 (the External Interrupt Request 0), etc. Table 3. Reset and Interrupt Vectors Vector No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Program Address $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D Source RESET INT0 INT1 TIMER1 CAPT TIMER1 COMP TIMER1 OVF TIMER0 OVF SPI, STC UART, RX UART, UDRE UART, TX ADC EE_RDY ANA_COMP Interrupt Definition External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset External Interrupt Request 0 External Interrupt Request 1 Timer/Counter1 Capture Event Timer/Counter1 Compare Match Timer/Counter1 Overflow Timer/Counter0 Overflow Serial Transfer Complete UART, Rx Complete UART Data Register Empty UART, Tx Complete ADC Conversion Complete EEPROM Ready Analog Comparator 20 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 The most typical program setup for the Reset and Interrupt Vector addresses are: Address $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d ; $00e $00f $010 ... ... MAIN: ldi out Reset Sources The AT90S4433 has four sources of reset: * * * * Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns. Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. Brown-out Reset. The MCU is reset when the supply voltage (VCC) falls below a certain voltage. During Reset, all I/O Registers are then set to their Initial Values, and the program starts execution from address $000. The instruction placed in address $000 must be an RJMP (relative jump) instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 24 shows the Reset Logic. Table 4 and Table 5 define the timing and electrical parameters of the reset circuitry. 21 1042H-AVR-04/03 Figure 24. Reset Logic DATA BUS MCU Status Register (MCUSR) VCC Power-on Reset Circuit BODEN BODLEVEL Brown-out Reset Circuit PORF BORF EXTRF WDRF RESET Reset Circuit Watchdog Timer CKSEL[2:0] On-chip RC Oscillator Delay Counters Full CK Table 4. Reset Characteristics (VCC = 5.0V) Symbol Parameter Power-on Reset Threshold Voltage, rising Power-on Reset Threshold Voltage, falling RESET Pin Threshold Voltage Brown-out Reset Threshold Voltage 2.2 (BODLEVEL=1) 3.5 (BODLEVEL=0) Min 1.0 Typ 1.4 Max 1.8 Units V VPOT(1) 0.4 0.6 Counter Reset 0.8 V VRST 0.6 VCC 2.7 (BODLEVEL=1) 4.0 (BODLEVEL=0) 3.0 (BODLEVEL=1) V VBOT V 4.5 (BODLEVEL=0) Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling). 22 AT90S/LS4433 1042H-AVR-04/03 Internal Reset AT90S/LS4433 Table 5. Reset Delay Selections CKSEL [2:0] 000 001 010 011 100 101 110 111 Note: Start-up Time, tTOUT at VCC = 2.7V 16 ms + 6 CK 6 CK 256 ms + 16K CK 16 ms + 16K CK 16K CK 256 ms + 1K CK 16 ms + 1K CK 1K CK 1. Or external Power-on Reset. Start-up Time, tTOUT at VCC = 5.0V 4 ms + 6 CK 6 CK 64 ms + 16K CK 4 ms + 16K CK 16K CK 64 ms + 1K CK 4 ms + 1K CK 1K CK Recommended Usage External Clock, slowly rising power External Clock, BOD enabled(1) Crystal Oscillator Crystal Oscillator, fast rising power Crystal Oscillator, BOD enabled(1) Ceramic Resonator Ceramic Resonator, fast rising power Ceramic Resonator, BOD enabled(1) This table shows the Start-up times from Reset. From sleep, only the clock counting part of the Start-up time is used. The Watchdog Oscillator is used for timing the Real Time part of the Start-up time. The number WDT Oscillator cycles used for each time-out is shown in Table 6. Table 6. Number of Watchdog Oscillator Cycles Time-out 4.0 ms (at VCC = 5.0V) 64 ms (at VCC = 5.0V) Number of Cycles 4K 64K The frequency of the Watchdog Oscillator is voltage dependent, as shown in the Electrical Characteristics section. Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip Detection circuit. The detection level is nominally 2.2V. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as detect a failure in supply voltage. The Power-on Reset (POR) circuit ensures that the device is Reset from Power-on. Reaching the Power-on Reset threshold voltage invokes a delay counter, which determines the delay, for which the device is kept in RESET after VCC rise. The Time-out period of the delay counter is a combination of Internal RC Oscillator cycles and External Oscillator cycles, and it can be defined by the user through the CKSEL Fuses. The eight different selections for the delay period are presented in Table 5. The RESET signal is activated again, without any delay, when the VCC decreases to below detection level. 23 1042H-AVR-04/03 Figure 25. MCU Start-up, RESET Tied to VCC VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET Figure 26. MCU Start-up, RESET Controlled Externally VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset. When the applied signal reaches the Reset Threshold Voltage (VRST) on its positive edge, the delay timer starts the MCU after the Time-out period (tTOUT) has expired. Figure 27. External Reset during Operation 24 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Brown-out Detection AT90S4433 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during the operation. The power supply must be decoupled with a 47 nF to 100 nF capacitor if the BOD function is used. The BOD circuit can be enabled/disabled by the fuse BODEN. When BODEN is enabled (BODEN programmed), and VCC decreases to a value below the trigger level, the Brown-out Reset is immediately activated. When VCC increases above the trigger level, the Brown-out Reset is deactivated after a delay. The delay is defined by the user in the same way as the delay of POR signal (see Table 5). The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis of 50 mV to ensure spike-free Brown-out Detection. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than 3 s for trigger level 4.0V, 7 s for trigger level 2.7V (typical values). Figure 28. Brown-out Reset during Operation VCC VBOTVBOT+ RESET TIME-OUT tTOUT INTERNAL RESET Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one XTAL cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period (tTOUT). See page 43 for details on operation of the Watchdog. Figure 29. Watchdog Reset during Operation 25 1042H-AVR-04/03 MCU Status Register - MCUSR The MCU Status Register provides information on which reset source caused an MCU Reset. Bit $34 ($54) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W See Bit Description 0 PORF R/W MCUSR * Bits 7..4 - Res: Reserved Bits These bits are reserved bits in the AT90S4433 and always read as zero. * Bit 3 - WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is cleared by a Power-On Reset, or by writing a logical "0" to the flag. * Bit 2 - BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is cleared by a Power-on Reset, or by writing a logical "0" to the flag. * Bit 1 - EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is cleared by a Power-on Reset, or by writing a logical "0" to the flag. * Bit 0 - PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is cleared only by writing a logical "0" to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then clear the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. Interrupt Handling The AT90S4433 has two 8-bit Interrupt Mask Control Registers; GIMSK (General Interrupt Mask) Register and TIMSK (Timer/Counter Interrupt Mask) Register. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed. When the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a logical "1" to the flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the Interrupt Flag will be set and remembered until the interrupt is enabled or the flag is cleared by software. If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared (zero), the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set (one), and will be executed by order of priority. Note that external level interrupt does not have a flag and will only be remembered for as long as the interrupt condition is active. 26 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Note that the Status Register is not automatically stored when entering an interrupt routine or restored when returning from an interrupt routine. This must be handled by software. General Interrupt Mask Register - GIMSK Bit $3B ($5B) Read/Write Initial Value 7 INT1 R/W 0 6 INT0 R/W 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIMSK * Bit 7 - INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU General Control Register (MCUCR) defines whether the External Interrupt is activated on rising or falling edge of the INT1 pin or is level sensed. Please note that INTF1 Flag is not set when the level-sensitive interrupt condition is met. However, INT1 interrupt is generated, provided that INT1 mask bit is set in GIMSK Register. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also "External Interrupts". * Bit 6 - INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU General Control Register (MCUCR) defines whether the External Interrupt is activated on rising or falling edge of the INT0 pin or is level sensed. Please note that INTF0 Flag is not set when the level-sensitive interrupt condition is met. However, INT0 interrupt is generated, provided that INT0 mask bit is set in GIMSK Register. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also "External Interrupts". * Bits 5..0 - Res: Reserved Bits These bits are reserved bits in the AT90S4433 and always read as zero. General Interrupt Flag Register - GIFR Bit $3A ($5A) Read/Write Initial Value 7 INTF1 R/W 0 6 INTF0 R/W 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIFR * Bit 7 - INTF1: External Interrupt Flag1 When an edge on the INT1 pin triggers an interrupt request, the corresponding interrupt flag, INTF1 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT1 in GIMSK, is set (one), the MCU will jump to the Interrupt Vector. The flag is always cleared when the interrupt routine is executed. Alternatively, the flag is cleared by writing a logical "1" to it. This flag is always cleared when INT1 is configured as level interrupt. 27 1042H-AVR-04/03 * Bit 6 - INTF0: External Interrupt Flag0 When an edge on the INT0 pin triggers an interrupt request, the corresponding Interrupt Flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT0 in GIMSK is set (one), the MCU will jump to the Interrupt Vector. The flag is always cleared when the interrupt routine is executed. Alternatively, the flag is cleared by writing a logical "1" to it. This flag is always cleared when INT0 is configured as level interrupt. * Bits 5..0 - Res: Reserved Bits These bits are reserved bits in the AT90S4433 and always read as zero. Timer/Counter Interrupt Mask Register - TIMSK Bit $39 ($59) Read/Write Initial Value 7 TOIE1 R/W 0 6 OCIE1 R/W 0 5 - R 0 4 - R 0 3 TICIE1 R/W 0 2 - R 0 1 TOIE0 R/W 0 0 - R 0 TIMSK * Bit 7 - TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding interrupt (at vector $005) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register (TIFR). * Bit 6 - OCIE1: Timer/Counter1 Output Compare Match Interrupt Enable When the OCIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare Match Interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a compare match in Timer/Counter1 occurs, i.e., when the OCF1 bit is set in the Timer/Counter Interrupt Flag Register (TIFR). * Bits 5, 4 - Res: Reserved Bits These bits are reserved bits in the AT90S4433 and always read as zero. * Bit 3 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 14, PB0 (ICP), i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register (TIFR). * Bit 2 - Res: Reserved Bit This bit is a reserved bit in the AT90S4433 and always reads as zero. * Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register (TIFR). * Bit 0 - Res: Reserved Bit This bit is a reserved bit in the AT90S4433 and always reads as zero. 28 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Timer/Counter Interrupt Flag Register - TIFR Bit $38 ($58) Read/Write Initial Value 7 TOV1 R/W 0 6 OCF1 R/W 0 5 - R 0 4 - R 0 3 ICF1 R/W 0 2 - R 0 1 TOV0 R/W 0 0 - R 0 TIFR * Bit 7 - TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logical "1" to the flag. When the I-bit in SREG and TOIE1 (Tim er/Co un ter1 Ove rflow Inte rrup t En able) an d TO V1 a re set (o ne) , th e Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 advances from $0000. * Bit 6 - OCF1: Output Compare Flag 1 The OCF1 bit is set (one) when a Compare Match occurs between the Timer/Counter1 and the data in Output Compare Register 1 (OCR1). OCF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1 is cleared by writing a logical "1" to the flag. When the I-bit in SREG and OCIE1 (Timer/Counter1 Compare Match Interrupt A Enable) and the OCF1 are set (one), the Timer/Counter1 Compare Match Interrupt is executed. * Bits 5, 4 - Res: Reserved Bits These bits are reserved bits in the AT90S4433 and always read as zero. * Bit 3 - ICF1: Input Capture Flag 1 The ICF1 bit is set (one) to flag an Input Capture Event, indicating that the Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logical "1" to the flag. When the SREG I-bit and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. * Bit 2 - Res: Reserved Bit This bit is a reserved bit in the AT90S4433 and always reads as zero. * Bit 1 - TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical "1" to the flag. When the SREG I-bit and TOIE0 (Tim er/Co un ter0 Ove rflow Inte rrup t En able) an d TO V0 a re set (o ne) , th e Timer/Counter0 Overflow Interrupt is executed. * Bit 0 - Res: Reserved Bit This bit is a reserved bit in the AT90S4433 and always reads as zero. 29 1042H-AVR-04/03 External Interrupts The External Interrupts are triggered by the INT1 and INT0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register (MCUCR). When the External Interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. The External Interrupts are set up as described in the specification for the MCU Control Register (MCUCR). Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. Four clock cycles after the Interrupt Flag has been set, the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter (two bytes) is pushed onto the Stack, and the Stack Pointer is decremented by two. The vector is normally a relative jump to the interrupt routine, and this jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. A return from an interrupt handling routine (same as for a subroutine call routine) takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two and the I-flag in SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. MCU Control Register - MCUCR The MCU Control Register contains control bits for general MCU functions. Bit $35 ($55) Read/Write Initial Value 7 - R 0 6 - R 0 5 SE R/W 0 4 SM R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR * Bits 7, 6 - Res: Reserved Bits These bits are reserved bits in the AT90S4433 and always read as zero. * Bit 5 - SE: Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid having the MCU entering the sleep mode unless it is the programmer's purpose, it is recommended that the Sleep Enable SE bit be set just before the execution of the SLEEP instruction. * Bit 4 - SM: Sleep Mode This bit selects between the two available sleep modes. When SM is cleared (zero), Idle mode is selected as sleep mode. When SM is set (one), Power-down mode is selected as sleep mode. For details, refer to the paragraph "Sleep Modes" below. 30 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 * Bits 3, 2 - ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the GIMSK are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 7. Table 7. Interrupt 1 Sense Control ISC11 0 0 1 1 ISC10 0 1 0 1 Description The low level of INT1 generates an interrupt request. Any logical change on INT1 generates an interrupt request. The falling edge of INT1 generates an interrupt request. The rising edge of INT1 generates an interrupt request. The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. * Bits 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 8. Table 8. Interrupt 0 Sense Control ISC01 0 0 1 1 ISC00 0 1 0 1 Description The low level of INT0 generates an interrupt request. Any logical change on INT0 generates an interrupt request. The falling edge of INT0 generates an interrupt request. The rising edge of INT0 generates an interrupt request. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. The SM bit in the MCUCR Register selects which sleep mode (Idle or Power-down) will be activated by the SLEEP instruction. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Note that if a level-triggered interrupt is used for wake-up from Power-down, the low level must be held for a time longer than the reset delay Time-out period (tTOUT). Otherwise, the device will not wake up. 31 1042H-AVR-04/03 Idle Mode When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle mode stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external triggered interrupts as well as internal ones like Timer Overflow interrupt and Watchdog Reset. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register (ACSR). This will reduce power consumption in Idle mode. When the SM bit is set (one), the SLEEP instruction forces the MCU into the Powerdown mode. In this mode, the External Oscillator is stopped while the external interrupts and the Watchdog (if enabled) continue operating. Only an External Reset, a Watchdog Reset (if enabled) or an external level interrupt can wake up the MCU. Note that if a level-triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for a time to wake up the MCU. This makes the MCU less sensitive to noise. The Wake-up period is equal to the clock-counting part of the Reset period (see Table 5). The MCU will wake up from Power-down if the input has the required level for two Watchdog Oscillator cycles. If the wake-up period is shorter than two Watchdog Oscillator cycles, the MCU will wake up if the input has the required level for the duration of the Wake-up period. If the wake-up condition disappears before the wake-up period has expired, the MCU will wake up from Power-down without executing the corresponding interrupt. The period of the Watchdog Oscillator is 2.7 s (nominal) at 3.0V and 25C. The frequency of the Watchdog Oscillator is voltage dependent as shown in the Electrical Characteristics section. When waking up from Power-down mode, a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period. Power-down Mode 32 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Timer/Counters The AT90S4433 provides two general purpose Timer/Counters - one 8-bit T/C and one 16-bit T/C. Timer/Counters0 and 1 have individual prescaling selection from the same 10-bit prescaling timer. These Timer/Counters can either be used as a Timer with an internal clock time base or as a counter with an external pin connection that triggers the counting. Figure 30. Prescaler for Timer/Counter0 and 1 Timer/Counter Prescaler TCK1 TCK0 For Timer/Counters0 and 1, the four different prescaled selections are CK/8, CK/64, CK/256, and CK/1024, where CK is the Oscillator clock. For the two Timer/Counters0 and 1, external source and stop can also be selected as clock sources. 8-bit Timer/Counter0 The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external pin. In addition, it can be stopped as described in the specification for the Timer/Counter0 Control Register (TCCR0). The Overflow Status Flag is found in the Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the Timer/Counter0 Control Register (TCCR0). The interrupt enable/disable settings for Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register (TIMSK). When Timer/Counter0 is externally clocked, the external signal is synchronized with the Oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high-accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions. Figure 31 shows the block diagram for Timer/Counter0. 33 1042H-AVR-04/03 Figure 31. Timer/Counter0 Block Diagram OCIE1 OCF1 T0 Timer/Counter0 Control Register - TCCR0 Bit $33 ($53) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0 * Bits 7 - 3 - Res: Reserved Bits These bits are reserved bits in the AT90S4433 and always read as zero. * Bits 2, 1, 0 - CS02, CS01, CS00: Clock Select0, Bits 2, 1, and 0 The Clock Select0 bits 2, 1, and 0 define the prescaling source of Timer/Counter0. Table 9. Clock 0 Prescale Select CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 Description Stop, Timer/Counter0 is stopped. CK CK/8 CK/64 CK/256 CK/1024 External Pin T0, falling edge External Pin T0, rising edge 34 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes are scaled directly from the CK Oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PD4/(T0) will clock the counter even if the pin is configured as an output. This feature can give the user software control of the counting. Timer Counter0 - TCNT0 Bit $32 ($52) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 TCNT0 The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation. 16-bit Timer/Counter1 Figure 32 shows the block diagram for Timer/Counter1. Figure 32. Timer/Counter1 Block Diagram T1 The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK or an external pin. In addition, it can be stopped as described in the specification for the Timer/Counter1 Control Register (TCCR1A). The different Status Flags (Overflow, Compare Match and Capture Event) and control signals are found in the Timer/Counter 35 1042H-AVR-04/03 Interrupt Flag Register (TIFR). The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register (TIMSK). When Timer/Counter1 is externally clocked, the external signal is synchronized with the Oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 16-bit Timer/Counter1 features both a high resolution and a high-accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities makes the Timer/Counter1 useful for lower speed functions or exact timing functions with infrequent actions. The Timer/Counter1 supports an Output Compare function using the Output Compare Register1 (OCR1) as the data source to be compared to the Timer/Counter1 contents. The Output Compare functions include optional clearing of the counter on compare matches and actions on the Output Compare pin 1 on compare matches. Timer/Counter1 can also be used as a 8-, 9-, or 10-bit Pulse Width Modulator. In this mode, the counter and the OCR1 Register serve as a glitch-free, stand-alone PWM with centered pulses. Refer to page 41 for a detailed description of this function. The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1 contents to the Input Capture Register (ICR1), triggered by an external event on the Input Capture Pin (ICP). The actual capture event settings are defined by the Timer/Counter1 Control Register (TCCR1). In addition, the Analog Comparator can be set to trigger the Input Capture. Refer to the section, "The Analog Comparator", for details of this. The ICP pin logic is shown in Figure 33. Figure 33. ICP Pin Schematic Diagram If the Noise Canceler function is enabled, the actual trigger condition for the capture event is monitored over four samples, and all four must be equal to activate the Capture Flag. The input pin signal is sampled at XTAL clock frequency. 36 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Timer/Counter1 Control Register A - TCCR1A Bit $2F ($4F) Read/Write Initial Value 7 COM11 R/W 0 6 COM10 R/W 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 PWM11 R/W 0 0 PWM10 R/W 0 TCCR1A * Bits 7, 6 - COM11, COM10: Compare Output Mode1, Bits 1, and 0 The COM11 and COM10 control bits determine any output pin action following a Compare Match in Timer/Counter1. Any output pin actions affect pin OC1 (Output Compare pin 1). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10. Table 10. Compare 1 Mode Select COM11 0 0 1 1 COM10 0 1 0 1 Description Timer/Counter1 disconnected from output pin OC1 Toggle the OC1 output line. Clear the OC1 output line (to zero). Set the OC1 output line (to one). In PWM mode, these bits have a different function. Refer to Table 11 for a detailed description. * Bits 5..2 - Res: Reserved Bits These bits are reserved bits in the AT90S4433 and always read as zero. * Bits 1, 0 - PWM11, PWM10: Pulse Width Modulator Select Bits These bits select PWM operation of Timer/Counter1 as specified in Table 11. This mode is described on page 41. Table 11. PWM Mode Select PWM11 0 0 1 1 PWM10 0 1 0 1 Description PWM operation of Timer/Counter1 is disabled Timer/Counter1 is an 8-bit PWM Timer/Counter1 is a 9-bit PWM Timer/Counter1 is a 10-bit PWM 37 1042H-AVR-04/03 Timer/Counter1 Control Register B - TCCR1B Bit $2E ($4E) Read/Write Initial Value 7 ICNC1 R/W 0 6 ICES1 R/W 0 5 - R 0 4 - R 0 3 CTC1 R/W 0 2 CS12 R/W 0 1 CS11 R/W 0 0 CS10 R/W 0 TCCR1B * Bit 7 - ICNC1: Input Capture1 Noise Canceler (4 CKs) When the ICNC1 bit is cleared (zero), the Input Capture trigger Noise Canceler function is disabled. The Input Capture is triggered at the first rising/falling edge sampled on the ICP (Input Capture Pin) as specified. When the ICNC1 bit is set (one), four successive samples are measured on the ICP (Input Capture Pin), and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is the XTAL clock frequency. * Bit 6 - ICES1: Input Capture1 Edge Select While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register (ICR1) on the falling edge of the Input Capture Pin (ICP). While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register (ICR1) on the rising edge of the Input Capture Pin (ICP). * Bits 5, 4 - Res: Reserved Bits These bits are reserved bits in the AT90S4433 and always read as zero. * Bit 3 - CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a Compare Match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a Compare Match. Since the compare match is detected in the CPU clock cycle following the match, this function will behave differently when a prescaling higher than 1 is used for the Timer. When a prescaling of 1 is used and the Compare Register is set to C, the timer will count as follows if CTC1 is set: ... | C-2 | C-1 | C | 0 | 1 | ... When the prescaler is set to divide by 8, the timer will count like this: ... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0, 0, 0, 0, 0, 0, 0 | 1, 1, 1, 1, 1, 1, 1, 1| ... In PWM mode, this bit has no effect. 38 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 * Bits 2, 1, 0 - CS12, CS11, CS10: Clock Select1, Bits 2, 1, and 0 The Clock Select1 bits 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 12. Clock 1 Prescale Select CS12 0 0 0 0 1 1 1 1 CS11 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 Description Stop, the Timer/Counter1 is stopped. CK CK/8 CK/64 CK/256 CK/1024 External Pin T1, falling edge External Pin T1, rising edge The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes are scaled directly from the CK Oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PD5/(T1) will clock the counter even if the pin is configured as an output. This feature can give the user software control of the counting. Timer/Counter1 - TCNT1H and TCNT1L Bit $2D ($4D) $2C ($4C) 15 MSB 14 13 12 11 10 9 8 TCNT1H LSB TCNT1L 7 Read/Write R/W R/W Initial Value 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 0 R/W R/W 0 0 This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the High and Low Bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1 and ICR1. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routines). * TCNT1 Timer/Counter1 Write When the CPU writes to the High Byte TCNT1H, the written data is placed in the TEMP Register. Next, when the CPU writes the Low Byte TCNT1L, this byte of data is combined with the byte data in the TEMP Register, and all 16 bits are written to the TCNT1 Timer/Counter1 Register simultaneously. Consequently, the High Byte TCNT1H must be accessed first for a full 16-bit register write operation. * TCNT1 Timer/Counter1 Read When the CPU reads the Low Byte TCNT1L, the data of the Low Byte TCNT1L is sent to the CPU and the data of the High Byte TCNT1H is placed in the TEMP Register. When the CPU reads the data in the High Byte TCNT1H, the CPU receives the data in 39 1042H-AVR-04/03 the TEMP Register. Consequently, the Low Byte TCNT1L must be accessed first for a full 16-bit register read operation. The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value. Timer/Counter1 Output Compare Register - OCR1H and OCR1L Bit $2B ($4B) $2A ($4A) 15 MSB 14 13 12 11 10 9 8 OCR1H LSB OCR1L 7 Read/Write R/W R/W Initial Value 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 0 R/W R/W 0 0 The Output Compare Register is a 16-bit read/write register. The Timer/Counter1 Output Compare Register contains the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status Register. Since the Output Compare Register (OCR1) is a 16-bit register, a temporary register TEMP is used when OCR1 is written to ensure that both bytes are updated simultaneously. When the CPU writes the High Byte, OCR1H, the data is temporarily stored in the TEMP Register. When the CPU writes the Low Byte, OCR1L, the TEMP Register is simultaneously written to OCR1H. Consequently, the High Byte OCR1H must be written first for a full 16-bit register write operation. The TEMP Register is also used when accessing TCNT1 and ICR1. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program. 40 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Timer/Counter1 Input Capture Register - ICR1H and ICR1L Bit $27 ($47) $26 ($46) 15 MSB 14 13 12 11 10 9 8 ICR1H LSB ICR1L 7 Read/Write R R Initial Value 0 0 6 R R 0 0 5 R R 0 0 4 R R 0 0 3 R R 0 0 2 R R 0 0 1 R R 0 0 0 R R 0 0 The Input Capture Register is a 16-bit, read only register. When the rising or falling edge (according to the input capture edge setting [ICES1]) of the signal at the Input Capture Pin (ICP) is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register (ICR1). At the same time, the Input Capture Flag (ICF1) is set (one). Since the Input Capture Register (ICR1) is a 16-bit register, a temporary register (TEMP) is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the Low Byte, ICR1L, the data is sent to the CPU and the data of the High Byte, ICR1H, is placed in the TEMP Register. When the CPU reads the data in the High Byte, ICR1H, the CPU receives the data in the TEMP Register. Consequently, the Low Byte, ICR1L, must be accessed first for a full 16-bit register read operation. The TEMP Register is also used when accessing TCNT1 and OCR1. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program. Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1 (OCR1) form a 8-, 9-, or 10-bit, free-running, glitch-free, phase correct PWM with output on the PB1(OC1) pin. Timer/Counter1 acts as an up/down counter, counting up from $0000 to TOP (see Table 13), where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the contents of the 8, 9, or 10 least significant bits of OCR1, the PB1(OC1) pin is set or cleared according to the settings of the COM11 and COM10 bits in the Timer/Counter1 Control Register (TCCR1). Refer to Table 14 for details. Table 13. Timer TOP Values and PWM Frequency(1) PWM Resolution 8-bit 9-bit 10-bit Note: Timer TOP Value $00FF (255) $01FF (511) $03FF(1023) Frequency fTCK1/510 fTCK1/1022 fTCK1/2046 1. If the Compare Register contains the TOP value and the prescaler is not in use (CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the up-counting and down-counting values are reached simultaneously. When the prescaler is in use (CS12..CS10 001 or 000), the PWM output goes active when the counter reaches the TOP value, but the down-counting compare match is not interpreted to be reached before the next time the counter reaches the TOP value, making a one-period PWM pulse. 41 1042H-AVR-04/03 Table 14. Compare1 Mode Select in PWM Mode COM11 0 0 1 1 COM10 0 1 0 1 Effect on OC1 Not connected Not connected Cleared on compare match, up-counting. Set on compare match, downcounting (non-inverted PWM). Cleared on compare match, down-counting. Set on compare match, upcounting (inverted PWM). Note that in the PWM mode, the ten least significant OCR1 bits, when written, are transferred to a temporary location. They are latched when Timer/Counter1 reaches TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1 write. See Figure 34 for an example. Figure 34. Effects on Unsynchronized OCR1 Latching During the time between the write and the latch operation, a read from OCR1 will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1. When OCR1 contains $0000 or TOP, the output OC1 is updated to low or high on the next compare match according to the settings of COM11 and COM10. This is shown in Table 15. Table 15. PWM Outputs OCR = $0000 or TOP COM11 1 1 1 1 COM10 0 0 1 1 OCR1 $0000 TOP $0000 TOP Output OC1 L H H L In PWM mode, the Timer Overflow Flag1 (TOV1) is set when the counter changes direction at $0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode, i.e., it is executed when TOV1 is set, provided that Timer Overflow Interrupt1 and global interrupts are enabled. This also applies to the Timer Output Compare1 Flag and interrupt. 42 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 6. See characterization data for typical values at other VCC levels. The WDR (Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the AT90S4433 resets and executes from the Reset vector. For timing details on the Watchdog Reset, refer to page 25. To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer Control Register for details. Figure 35. Watchdog Timer Watchdog Timer Control Register - WDTCR Bit $21 ($41) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 WDTOE R/W 0 3 WDE R/W 0 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCR * Bits 7..5 - Res: Reserved Bits These bits are reserved bits in the AT90S4433 and will always read as zero. * Bit 4 - WDTOE: Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. * Bit 3 - WDE: Watchdog Enable When the WDE is set (one), the Watchdog Timer is enabled; if the WDE is cleared (zero), the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logical "1" to WDTOE and WDE. A logical "1" must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical "0" to WDE. This disables the Watchdog. 43 1042H-AVR-04/03 * Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0 The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding time-out periods are shown inTable 16. Table 16. Watchdog Timer Prescale Select(1) WDP2 0 0 0 0 1 1 1 1 Note: WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 Number of WDT Oscillator Cycles 16K cycles 32K cycles 64K cycles 128K cycles 256K cycles 512K cycles 1,024K cycles 2,048K cycles Typical Time-out at VCC = 3.0V 47 ms 94 ms 0.19 s 0.38 s 0.75 s 1.5 s 3.0 s 6.0 s Typical Time-out at VCC = 5.0V 15 ms 30 ms 60 ms 0.12 s 0.24 s 0.49 s 0.97 s 1.9 s 1. The frequency of the Watchdog Oscillator is voltage dependent, as shown in the Electrical Characteristics section. The WDR (Watchdog Reset) instruction should always be executed before the Watchdog Timer is enabled. This ensures that the reset period will be in accordance with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the Watchdog Timer may not start counting from zero. To avoid unintentional MCU reset, the Watchdog Timer should be disabled or Reset before changing the Watchdog Timer Prescale Select. 44 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time is in the range of 2.5 - 4 ms, depending on the VCC voltages. A self-timing function lets the user software detect when the next byte can be written. A special EEPROM Ready interrupt can be set to trigger when the EEPROM is ready to accept new data. An ongoing EEPROM write operation will complete even if a reset condition occurs. In order to prevent unintentional EEPROM writes, a two-state write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. EEPROM Address Register - EEAR Bit $1E ($3E) 7 EEAR7 6 EEAR6 5 EEAR5 4 EEAR4 3 EEAR3 2 EEAR2 1 EEAR1 0 EEAR0 EEAR Read/Write Initial Value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X The EEPROM Address Register (EEAR) specifies the EEPROM address in the 256 bytes of EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 255. The Initial Value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. EEPROM Data Register - EEDR Bit $1D ($3D) Read/Write Initial Value 7 MSB R/W 0 6 5 4 3 2 1 0 LSB EEDR R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 * Bits 7..0 - EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. EEPROM Control Register - EECR Bit $1C ($3C) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 EERIE R/W 0 2 EEMWE R/W 0 1 EEWE R/W 0 0 EERE R/W 0 EECR * Bits 7..4 - Res: Reserved Bits These bits are reserved bits in the AT90S4433 and will always read as zero. 45 1042H-AVR-04/03 * Bit 3 - EERIE: EEPROM Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero). * Bit 2 - EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure. * Bit 1 - EEWE: EEPROM Write Enable The EEPROM Write Enable Signal (EEWE) is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical "1" is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEAR (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical "1" to the EEMWE bit in EECR (to be able to write a logical "1" to the EEMWE bit, the EEWE bit must be written to zero in the same cycle). 5. Within four clock cycles after setting EEMWE, write a logical "1" to EEWE. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR and EEDR Registers will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the last four steps to avoid these problems. When the write access time (typically 2.5 ms at VCC = 5V or 4 ms at VCC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. * Bit 0 - EERE: EEPROM Read Enable The EEPROM Read Enable Signal (EERE) is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR Register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O Registers, the write operation will be interrupted and the result is undefined. 46 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Prevent EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board-level systems using the EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Second, the CPU itself can execute instructions incorrectly if the supply voltage for executing instructions is too low. EEPROM data corruption can easily be avoided by following these design recommendations (one is sufficient): 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating speed matches the detection level. If not, an external low VCC Reset Protection circuit can be applied. 2. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the EEPROM Registers from unintentional writes. 3. Store constants in Flash memory if the ability to change memory contents from software is not required. Flash memory cannot be updated by the CPU and will not be subject to corruption. 47 1042H-AVR-04/03 Serial Peripheral Interface - SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S4433 and peripheral devices or between several AVR devices. The AT90S4433 SPI features include the following: * Full Duplex, Three-wire Synchronous Data Transfer * Master or Slave Operation * LSB First or MSB First Data Transfer * Four Programmable Bit Rates * End of Transmission Interrupt Flag * Write Collision Flag Protection * Wake-up from Idle Mode Figure 36. SPI Block Diagram The interconnection between Master and Slave CPUs with SPI is shown in Figure 37. The PB5(SCK) pin is the clock output in the Master mode and is the clock input in the Slave mode. Writing to the SPI Data Register of the Master CPU starts the SPI clock generator, and the data written shifts out of the PB3(MOSI) pin and into the PB3(MOSI) pin of the Slave CPU. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Slave Select input, PB2(SS), is set low to select an individual Slave SPI device. The two Shift Registers in the Master and the Slave can be considered as one distributed 16-bit circular Shift Register. This is shown in Figure 37. When data is shifted from the Master to the Slave, data is also shifted in the opposite direction, simultaneously. This means that during one shift cycle, data in the master and the slave are interchanged. 48 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Figure 37. SPI Master-slave Interconnection The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received byte must be read from the SPI Data Register before the next byte has been completely shifted in. Otherwise, the first byte is lost. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 17. Table 17. SPI Pin Direction Overrides(1) Pin MOSI MISO SCK SS Note: Direction Overrides, Master SPI Mode User Defined Input User Defined User Defined Direction Overrides, Slave SPI Modes Input User Defined Input Input 1. See "Alternate Functions of Port B" on page 73 for a detailed description of how to define the direction of the user-defined SPI pins. SS Pin Functionality When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin. If SS is configured as an output, the pin is a general output pin, which does not affect the SPI system. If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as master with the SS pin defined as an input, the SPI system interprets this as another master selecting the SPI as a slave and starts to send data to it. To avoid bus contention, the SPI system takes the following actions: 1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becoming a Slave, the MOSI and SCK pins become inputs. 2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled and the I-bit in SREG is set, the interrupt routine will be executed. Thus, when interrupt-driven SPI transmittal is used in Master mode, and there exists a possibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. Once the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable the SPI Master mode. When the SPI is configured as a slave, the SS pin is always input. When SS is held low, the SPI is activated and MISO becomes an output if configured so by the user. All other 49 1042H-AVR-04/03 pins are inputs. When SS is driven high, externally all pins are inputs and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI will stop sending and receiving immediately and both data received and data sent must be considered as lost. Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 38 and Figure 39. Figure 38. SPI Transfer Format with CPHA = 0 and DORD = 0 Figure 39. SPI Transfer Format with CPHA = 1 and DORD = 0 50 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 SPI Control Register - SPCR Bit $0D ($2D) Read/Write Initial Value 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 0 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR * Bit 7 - SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the global interrupts are enabled. * Bit 6 - SPE: SPI Enable When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations. * Bit 5 - DORD: Data Order When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. * Bit 4 - MSTR: Master/Slave Select This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared and SPIF in SPSR will become set. The user will then have to set MSTR to reenable SPI Master mode. * Bit 3 - CPOL: Clock Polarity When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 38 and Figure 39 for additional information. * Bit 2 - CPHA: Clock Phase Refer to Figure 38 or Figure 39 for the functionality of this bit. * Bits 1, 0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator clock frequency (fcl) is shown in Table 18. Table 18. Relationship between SCK and the Oscillator Frequency SPR1 0 0 1 1 SPR0 0 1 0 1 SCK Frequency fcl/4 fcl/16 fcl/64 fcl/128 51 1042H-AVR-04/03 SPI Status Register - SPSR Bit $0E ($2E) Read/Write Initial Value 7 SPIF R 0 6 WCOL R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 SPSR * Bit 7 - SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set (one), then by accessing the SPI Data Register (SPDR). * Bit 6 - WCOL: Write Collision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register with WCOL set (one), and then by accessing the SPI Data Register. * Bits 5..0 - Res: Reserved Bits These bits are reserved bits in the AT90S4433 and will always read as zero. The SPI interface on the AT90S4433 is also used for Program memory and EEPROM downloading or uploading. See page 93 for Serial Programming and verification. SPI Data Register - SPDR Bit $0F ($2F) Read/Write Initial Value 7 MSB R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 LSB R/W X Undefined SPDR The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. 52 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 UART The AT90S4433 features a full duplex (separate Receive and Transmit Registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are: * Baud Rate Generator Generates any Baud Rate * High Baud Rates at Low XTAL Frequencies * 8 or 9 Bits Data * Noise Filtering * Overrun Detection * Framing Error Detection * False Start Bit Detection * Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete * Multi-processor Communication Mode A block schematic of the UART Transmitter is shown in Figure 40. Figure 40. UART Transmitter Data Transmission UART CONTROL AND STAUS REGISTER B (UCSRB) UART CONTROL AND STAUS REGISTER A (UCSRA) Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register (UDR). Data is transferred from UDR to the Transmit Shift Register when: * * A new character has been written to UDR after the stop bit from the previous character has been shifted out. The Shift Register is loaded immediately. A new character has been written to UDR before the stop bit from the previous character has been shifted out. The Shift Register is loaded when the stop bit of the character currently being transmitted has been shifted out. When data is transferred from UDR to the Shift Register, the UDRE (UART Data Register Empty) bit in the UART Control and Status Register A, UCSRA, is set. When this bit is set (one), the UART is ready to receive the next character. At the same time as the 53 1042H-AVR-04/03 data is transferred from UDR to the 10(11)-bit Shift Register, bit 0 of the Shift Register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9 bit in the UART Control and Status Register B, UCSRB is set), the TXB8 bit in UCSRB is transferred to bit nine in the Transmit Shift Register. On the baud rate clock following the transfer operation to the Shift Register, the start bit is shifted out on the TXD pin. Then follows the data, LSB first. When the stop bit has been shifted out, the Shift Register is loaded if any new data has been written to the UDR during the transmission. During loading, UDRE is set. If there is no new data in the UDR Register to send when the stop bit is shifted out, the UDRE Flag will remain set until UDR is written again. When no new data has been written, and the stop bit has been present on TXD for one bit length, the TX Complete Flag, TXC, in UCSRA is set. The TXEN bit in UCSRB enables the UART Transmitter when set (one). When this bit is cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART Transmitter will be connected to PD1, which is forced to be an output pin regardless of the setting of the DDD1 bit in DDRD. Data Reception Figure 41 shows a block diagram of the UART Receiver. Figure 41. UART Receiver UART CONTROL AND STAUS REGISTER A (UCSRA) UART CONTROL AND STAUS REGISTER B (UCSRB) 54 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 The Receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical "0" will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample. Following the 1-to-0 transition, the Receiver samples the RXD pin at samples 8, 9, and 10. If two or more of these three samples are found to be logical "1"s, the start bit is rejected as a noise spike and the receiver starts looking for the next 1-to-0 transition. If, however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also sampled at samples 8, 9, and 10. The logical value found in at least two of the three samples is taken as the bit value. All bits are shifted into the transmitter Shift Register as they are sampled. Sampling of an incoming character is shown in Figure 42. Figure 42. Sampling Received Data When the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit. If two or more samples are logical "0"s, the Framing Error (FE) Flag in the UART Control and Status Register A (UCSRA) is set. Before reading the UDR Register, the user should always check the FE bit to detect Framing Errors. Whether or not a valid stop bit is detected at the end of a character reception cycle, the data is transferred to UDR and the RXC Flag in UCSRA is set. UDR is, in fact, two physically separate registers: one for Transmitted Data and one for Received Data. When UDR is read, the Receive Data Register is accessed, and when UDR is written, the Transmit Data Register is accessed. If 9-bit data word is selected (the CHR9 bit in the UART Control and Status Register B, UCSRB is set), the RXB8 bit in UCSRB is loaded with bit nine in the Transmit Shift Register when data is transferred to UDR. If, after having received a character, the UDR Register has not been read since the last receive, the OverRun (OR) Flag in UCSRB is set. This means that the last data byte shifted into the Shift Register could not be transferred to UDR and has been lost. The OR bit is buffered and is updated when the valid data byte in UDR is read. Thus, the user should always check the OR bit after reading the UDR Register in order to detect any overruns if the baud rate is high or CPU load is high. When the RXEN bit in the UCSRB Register is cleared (zero), the receiver is disabled. This means that the PD0 pin can be used as a general I/O pin. When RXEN is set, the UART receiver will be connected to PD0, which is forced to be an input pin regardless of the setting of the DDD0 bit in DDRD. When PD0 is forced to input by the UART, the PORTD0 bit can still be used to control the pull-up resistor on the pin. When the CHR9 bit in the UCSRB Register is set, transmitted and received characters are nine bits long, plus start and stop bits. The ninth data bit to be transmitted is the TXB8 bit in UCSRB Register. This bit must be set to the wanted value before a transmission is initiated by writing to the UDR Register. The ninth data bit received is the RXB8 bit in the UCSRB Register. 55 1042H-AVR-04/03 Multi-processor Communication Mode The Multi-processor Communication mode enables several slave MCUs to receive data from a Master MCU. This is done by first decoding an address byte to find out which MCU has been addressed. If a particular slave MCU has been addressed, it will receive the following data bytes as normal, while the other slave MCUs will ignore the data bytes until another address byte is received. For an MCU to act as a Master MCU, it should enter 9-bit Transmission mode (CHR9 in UCSRB set). The ninth bit must be one to indicate that an address byte is being transmitted, and zero to indicate that a data byte is being transmitted. For the Slave MCUs, the mechanism appears slightly differently for 8-bit and 9-bit Reception mode. In 8-bit Reception mode (CHR9 in UCSRB cleared), the stop bit is one for an address byte and zero for a data byte. In 9-bit Reception mode (CHR9 in UCSRB set), the ninth bit is one for an address byte and zero for a data byte, whereas the stop bit is always high. The following procedure should be used to exchange data in Multi-processor Communication mode: 1. All slave MCUs are in Multi-processor Communication mode (MPCM in UCSRA is set). 2. The Master MCU sends an address byte, and all Slaves receive and read this byte. In the slave MCUs, the RXC Flag in UCSRA will be set as normal. 3. Each Slave MCU reads the UDR Register and determines if it has been selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte. 4. For each received data byte, the receiving MCU will set the Receive Complete Flag (RXC in UCSRA). In 8-bit mode, the receiving MCU will also generate a Framing Error (FE in UCSRA set), since the stop bit is zero. The other Slave MCUs, which still have the MPCM bit set, will ignore the data byte. In this case, the UDR Register and the RXC or FE Flags will not be affected. 5. After the last byte has been transferred, the process repeats from step 2. 56 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 UART Control UART I/O Data Register - UDR Bit $0C ($2C) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 UDR The UDR Register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data Register is written. When reading from UDR, the UART Receive Data Register is read. UART Control and Status Register A - UCSRA Bit $0B ($2B) Read/Write Initial Value 7 RXC R 0 6 TXC R/W 0 5 UDRE R 1 4 FE R 0 3 OR R 0 2 - R 0 1 - R 0 0 MPCM R/W 0 UCSRA * Bit 7 - RXC: UART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift Register to UDR. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCSRB is set, the UART Receive Complete interrupt will be executed when RXC is set (one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates. * Bit 6 - TXC: UART Transmit Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift Register has been shifted out and no new data has been written to UDR. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter Receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCSRB is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical "1" to the bit. * Bit 5 - UDRE: UART Data Register Empty This bit is set (one) when a character written to UDR is transferred to the Transmit Shift Register. Setting of this bit indicates that the Transmitter is ready to receive a new character for transmission. When the UDRIE bit in UCSRB is set, the UART Transmit Complete interrupt to be executed as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready. 57 1042H-AVR-04/03 * Bit 4 - FE: Framing Error This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one. * Bit 3 - OR: OverRun This bit is set if an OverRun condition is detected, i.e., when a character already present in the UDR Register is not read before the next character has been shifted into the Receiver Shift Register. The OR bit is buffered, which means that it will be set once the valid data still in UDRE is read. The OR bit is cleared (zero) when data is received and transferred to UDR. * Bits 2..1 - Res: Reserved Bits These bits are reserved bits in the AT90S4433 and will always read as zero. * Bit 0 - MPCM: Multi-processor Communication Mode This bit is used to enter Multi-processor Communication mode. The bit is set when the slave MCU waits for an address byte to be received. When the MCU has been addressed, the MCU switches off the MPCM bit and starts data reception. For a detailed description, see "Multi-processor Communication Mode". UART Control and Status Register B - UCSRB Bit $0A ($2A) Read/Write Initial Value 7 RXCIE R/W 0 6 TXCIE R/W 0 5 UDRIE R/W 0 4 RXEN R/W 0 3 TXEN R/W 0 2 CHR9 R/W 0 1 RXB8 R 1 0 TXB8 W 0 UCSRB * Bit 7 - RXCIE: RX Complete Interrupt Enable When this bit is set (one), a setting of the RXC bit in UCSRA will cause the Receive Complete Interrupt routine to be executed, provided that global interrupts are enabled. * Bit 6 - TXCIE: TX Complete Interrupt Enable When this bit is set (one), a setting of the TXC bit in UCSRA will cause the Transmit Complete Interrupt routine to be executed, provided that global interrupts are enabled. * Bit 5 - UDRIE: UART Data Register Empty Interrupt Enable When this bit is set (one), a setting of the UDRE bit in UCSRA will cause the UART Data Register Empty Interrupt routine to be executed, provided that global interrupts are enabled. * Bit 4 - RXEN: Receiver Enable This bit enables the UART Receiver when set (one). When the Receiver is disabled, the RXC, OR, and FE status flags cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared. 58 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 * Bit 3 - TXEN: Transmitter Enable This bit enables the UART Transmitter when set (one). When disabling the Transmitter while transmitting a character, the Transmitter is not disabled before the character in the Shift Register plus any following character in UDR has been completely transmitted. * Bit 2 - CHR9: 9-bit Characters When this bit is set (one), transmitted and received characters are nine bits long, plus start and stop bits. The ninth bit is read and written by using the RXB8 and TXB8 bits in UCSRB, respectively. The ninth data bit can be used as an extra stop bit or a parity bit. * Bit 1 - RXB8: Receive Data Bit 8 When CHR9 is set (one), RXB8 is the ninth data bit of the received character. * Bit 0 - TXB8: Transmit Data Bit 8 When CHR9 is set (one), TXB8 is the ninth data bit in the character to be transmitted. Baud Rate Generator The Baud Rate Generator is a frequency divider, which generates baud rates according to the following equation: f CK BAUD = --------------------------------16(UBR + 1 ) * * * BAUD = Baud Rate fCK= Crystal Clock frequency UBR = Contents of the UBRRHI and UBRR Registers, (0 - 4095) For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBR settings in Table 19. UBR values that yield an actual baud rate differing less than 2% from the target baud rate are boldface in the table. However, using baud rates that have more than 1% error is not recommended. High error ratings give less noise resistance. 59 1042H-AVR-04/03 Table 19. UBR Settings at Various Crystal Frequencies Baud Rate 1 MHz %Error 1.8432 MHz %Error 2 MHz %Error 2.4576 MHz %Error 2400 UBR= 25 0.2 UBR= 47 0.0 UBR= 51 0.2 UBR= 63 0.0 4800 UBR= 12 0.2 UBR= 23 0.0 UBR= 25 0.2 UBR= 31 0.0 6 7.5 UBR= 9600 UBR= 11 0.0 UBR= 12 0.2 UBR= 15 0.0 UBR= 3 7.8 UBR= UBR= 8 3.7 UBR= 10 3.1 14400 7 0.0 2 7.8 UBR= 6 7.5 UBR= 19200 UBR= 5 0.0 UBR= 7 0.0 1 7.8 UBR= 3 7.8 UBR= 4 6.3 28800 UBR= 3 0.0 UBR= 1 22.9 UBR= 2 7.8 UBR= 38400 UBR= 2 0.0 UBR= 3 0.0 0 7.8 UBR= 1 7.8 UBR= 2 12.5 57600 UBR= 1 0.0 UBR= 0 22.9 UBR= 1 33.3 UBR= 1 22.9 UBR= 76800 UBR= 1 0.0 0 84.3 UBR= 0 7.8 UBR= 0 25.0 115200 UBR= 0 0.0 UBR= Baud Rate 3.2768 MHz %Error 3.6864 MHz %Error 4 MHz %Error 4.608 MHz %Error 2400 UBR= 84 0.4 UBR= 95 0.0 UBR= 103 0.2 UBR= 119 0.0 4800 UBR= 42 0.8 UBR= 47 0.0 UBR= 51 0.2 UBR= 59 0.0 9600 UBR= 20 1.6 UBR= 23 0.0 UBR= 25 0.2 UBR= 29 0.0 16 2.1 UBR= 14400 UBR= 13 1.6 UBR= 15 0.0 UBR= 19 0.0 10 3.1 UBR= 19200 UBR= 11 0.0 UBR= 12 0.2 UBR= 14 0.0 8 3.7 UBR= 28800 UBR= 6 1.6 UBR= 7 0.0 UBR= 9 0.0 4 6.3 UBR= 6 7.5 UBR= 7 6.7 38400 UBR= 5 0.0 UBR= 3 12.5 UBR= 3 7.8 UBR= 57600 UBR= 3 0.0 UBR= 4 0.0 UBR= 2 12.5 UBR= UBR= 2 7.8 UBR= 3 6.7 76800 2 0.0 1 12.5 UBR= 1 7.8 UBR= 2 20.0 115200 UBR= 1 0.0 UBR= Baud Rate 7.3728 MHz %Error 8 MHz %Error 9.216 MHz %Error 11.059 MHz %Error UBR= UBR= UBR= 287 2400 191 0.0 207 0.2 239 0.0 UBR= 4800 UBR= 95 0.0 UBR= 103 0.2 UBR= 119 0.0 UBR= 143 0.0 9600 UBR= 47 0.0 UBR= 51 0.2 UBR= 59 0.0 UBR= 71 0.0 14400 UBR= 31 0.0 UBR= 34 0.8 UBR= 39 0.0 UBR= 47 0.0 19200 UBR= 23 0.0 UBR= 25 0.2 UBR= 29 0.0 UBR= 35 0.0 16 2.1 UBR= 28800 UBR= 15 0.0 UBR= 19 0.0 UBR= 23 0.0 38400 UBR= 11 0.0 UBR= 12 0.2 UBR= 14 0.0 UBR= 17 0.0 8 3.7 UBR= 57600 UBR= 7 0.0 UBR= 9 0.0 UBR= 11 0.0 6 7.5 UBR= 7 6.7 UBR= 76800 UBR= 5 0.0 UBR= 8 0.0 3 7.8 UBR= 115200 UBR= 3 0.0 UBR= 4 0.0 UBR= 5 0.0 60 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 UART Baud Rate Register - UBRR Bit $03 ($23) $09 ($29) 15 - MSB 7 14 - 13 - 12 - 11 MSB 10 9 8 LSB LSB UBRRHI UBRR 6 R R/W 0 0 5 R R/W 0 0 4 R R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 0 R/W R/W 0 0 Read/Write R R/W Initial Value 0 0 This is a 12-bit register that contains the UART Baud Rate according to the equation on the previous page. The UBRRHI contains the four most significant bits, and the UBRR contains the eight least significant bits of the UART Baud Rate. 61 1042H-AVR-04/03 Analog Comparator The Analog Comparator compares the input values on the positive input PD6 (AIN0) and negative input PD7 (AIN1). When the voltage on the positive input PD6 (AIN0) is higher than the voltage on the negative input PD7 (AIN1), the Analog Comparator Output, ACO, is set (one). The comparator's output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 43. Figure 43. Analog Comparator Block Diagram Analog Comparator Control and Status Register - ACSR Bit $08 ($28) Read/Write Initial Value 7 ACD R/W 0 6 AINBG R/W 0 5 ACO R N/A 4 ACI R/W 0 3 ACIE R/W 0 2 ACIC R/W 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR * Bit 7 - ACD: Analog Comparator Disable When this bit is set (one), the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. When changing the ACD bit, the Analog Comparator interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise, an interrupt can occur when the bit is changed. * Bit 6 - AINBG: Analog Comparator Bandgap Select When this bit is set, BOD is enabled and the BODEN is programmed, a fixed bandgap voltage of 1.22V 0.1V replaces the normal input to the positive input (AIN0) of the comparator. When this bit is cleared, the normal input pin, PD6, is applied to the positive input of the comparator. * Bit 5 - ACO: Analog Comparator Output ACO is directly connected to the comparator output. 62 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 * Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logical "1" to the flag. * Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Comparator interrupt is activated. When cleared (zero), the interrupt is disabled. * Bit 2 - ACIC: Analog Comparator Input Capture Enable When set (one), this bit enables the Input Capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is, in this case, directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When cleared (zero), no connection between the Analog Comparator and the Input Capture function is given. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one). * Bits 1, 0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events trigger the Analog Comparator interrupt. The different settings are shown in Table 20. Table 20. ACIS1/ACIS0 Settings(1) ACIS1 0 0 1 1 Note: ACIS0 0 1 0 1 Interrupt Mode Comparator Interrupt on Output Toggle. Reserved Comparator Interrupt on Falling Output Edge. Comparator Interrupt on Rising Output Edge. 1. When changing the ACIS1/ACIS0 bits, the Analog Comparator interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise, an interrupt can occur when the bits are changed. Caution: Using the SBI or CBI instruction on bits other than ACI in this register will write a one back into ACI if it is read as set, thus clearing the flag. 63 1042H-AVR-04/03 Analog-to-Digital Converter Features * * * * * * * * * * 10-bit Resolution 2 LSB Absolute Accuracy 0.5 LSB Integral Non-linearity 65 - 260 s Conversion Time Up to 15 kSPS Six Multiplexed Input Channels Rail-to-Rail Input Range Free Run or Single Conversion Mode Interrupt on ADC Conversion Complete Sleep Mode Noise Canceler The AT90S4433 features a 10-bit successive approximation ADC. The ADC is connected to a 6-channel Analog Multiplexer, which allows each pin of Port C to be used as an input for the ADC. The ADC contains a Sample and Hold Amplifier, which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 44. The ADC has two separate analog supply voltage pins: AVCC and AGND. AGND must be connected to GND, and the voltage on AVCC must not differ from VCC more than 0.3V. See the section "ADC Noise Canceling Techniques" on page 70 for how to connect these pins. An external reference voltage must be applied to the AREF pin. This voltage must be in the range 2.0 - AVCC. Figure 44. Analog-to-Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ 8-BIT DATA BUS External Reference Voltage ADIF ADIE 9 ADC DATA REGISTER (ADCH/ADCL) 0 ADC MULTIPLEXER SELECT (ADMUX) MUX2 MUX1 MUX0 ADC CTRL & STATUS REGISTER (ADCSR) ADEN ADSC ADFR ADIE ADIF ADPS2 ADPS1 ADPS0 10-BIT DAC CONVERSION LOGIC Analog Inputs 6CHANNEL MUX + SAMPLE & HOLD COMPARATOR 64 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Operation The ADC can operate in two modes: Single Conversion and Free Run mode. In Single Conversion mode, each conversion will have to be initiated by the user. In Free Run mode, the ADC is constantly sampling and updating the ADC Data Register. The ADFR bit in ADCSR selects between the two available modes. The ADMUX Register selects which one of the six analog input channels is to be used as input to the ADC. The ADC is enabled by writing a logical "1" to the ADC Enable bit, ADEN in ADCSR. The first conversion that is started after enabling the ADC will be preceded by a dummy conversion to initialize the ADC. To the user, the only difference will be that this conversion takes 12 clock cycles more than a normal conversion. A conversion is started by writing a logical "1" to the ADC Start Conversion bit, ADSC. This bit will stay high as long as the conversion is in progress and be set to zero by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. As the ADC generates a 10-bit result, two Data Registers, ADCH and ADCL, must be read to get the result when the conversion is complete. Special data protection logic is used to ensure that the contents of the Data Registers belong to the same result when they are read. This mechanism works as follows: When reading data, ADCL must be read first. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read and a conversion completes before ADCH is read, none of the registers are updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt, ADIF, which can be triggered when a conversion completes. When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result gets lost. Prescaling Figure 45. ADC Prescaler ADEN CK Reset 7-BIT ADC PRESCALER ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE The ADC contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. The ADC accepts input clock frequencies in the range 50 - 200 kHz. Applying a higher input frequency will result in a poorer accuracy (see "ADC Characteristics" on page 71). The ADPS0 - ADPS2 bits in ADCSR are used to generate a proper ADC clock input frequency from any XTAL frequency above 100 kHz. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler CK/128 CK/16 CK/32 CK/64 CK/2 CK/4 CK/8 65 1042H-AVR-04/03 keeps running for as long as the ADEN bit is set and is continuously reset when ADEN is low. When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following rising edge of the ADC clock cycle. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of the conversion. The result is ready and written to the ADC Result Register after 13 cycles. In Single Conversion mode, the ADC needs one more clock cycle before a new conversion can be started (see Figure 47). If ADSC is set high in this period, the ADC will start the new conversion immediately. In Free Run mode, a new conversion will be started immediately after the result is written to the ADC Result Register. Using Free Run mode and an ADC clock frequency of 200 kHz gives the lowest conversion time, 65 s, equivalent to 15.4 kSPS. For a summary of conversion times, see Table 21. Figure 46. ADC Timing Diagram, First Conversion (Single Conversion Mode) Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 ADC Clock ADEN ADSC Hold Strobe ADIF ADCH ADCL MSB of Result LSB of Result Dummy Conversion Actual Conversion Second Conversion Table 21. ADC Conversion Time Condition 1st Conversion, Free Run 1st Conversion, Single Free Run Conversion Single Conversion Sample Cycle Number 13.5 13.5 1.5 1.5 Result Ready(Cycle Number) 25 25 13 13 Total Conversion Time (Cycles) 25 26 13 14 Total Conversion Time (s) 125 - 500 130 - 520 65 - 260 70 - 280 66 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Figure 47. ADC Timing Diagram, Single Conversion One Conversion Next Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion complete MUX and REFS Update Figure 48. ADC Timing Diagram, Free Run Conversion Cycle Number ADC Clock ADSC Hold Strobe ADIF ADCH ADCL MSB of Result LSB of Result 11 12 13 1 2 One Conversion Next Conversion ADC Noise Canceler Function The ADC features a Noise Canceler that enables conversion during Idle mode to reduce noise induced from the CPU core. To make use of this feature, the following procedure should be used: 1. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. Thus: ADEN = 1 ADSC = 0 ADFR = 0 ADIE = 1 2. Enter Idle mode. The ADC will start a conversion once the CPU has been halted. 3. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the MCU and execute the ADC conversion complete interrupt routine. 67 1042H-AVR-04/03 ADC Multiplexer Select Register - ADMUX Bit $07 ($27) Read/Write Initial Value 7 - R 0 6 ADCBG R/W 0 5 - R 0 4 - R 0 3 - R 0 2 MUX2 R/W 0 1 MUX1 R/W 0 0 MUX0 R/W 0 ADMUX * Bit 7 - Res: Reserved Bit This bit is a reserved bit in the AT90S4433, and should be written to zero if accessed. * Bit 6 - ADCBG: ADC Bandgap Select When this bit is set and the BOD is enabled (BODEN Fuse is programmed), a fixed bandgap voltage of 1.22V 0.1V replaces the normal input to the ADC. When this bit is cleared, the normal input pin (as selected by MUX2..MUX0) is applied to the ADC. * Bits 5..3 - Res: Reserved Bits These bits are reserved bits in the AT90S4433, and should be written to zero if accessed. * Bits 2..0 - MUX2..MUX0: Analog Channel Select Bits 2 - 0 The value of these three bits selects which analog input 5 - 0 is connected to the ADC. ADC Control and Status Register - ADCSR ` Bit $06 ($26) Read/Write Initial Value 7 ADEN R/W 0 6 ADSC R/W 0 5 ADFR R/W 0 4 ADIF R/W 0 3 ADIE R/W 0 2 ADPS2 R/W 0 1 ADPS1 R/W 0 0 ADPS0 R/W 0 ADCSR * Bit 7 - ADEN: ADC Enable Writing a logical "1" to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress will terminate this conversion. * Bit 6 - ADSC: ADC Start Conversion In Single Conversion mode, a logical "1" must be written to this bit to start each conversion. In Free Run mode, a logical "1" must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, a dummy conversion will precede the initiated conversion. This dummy conversion performs initialization of the ADC. ADSC remains high during the conversion. ADSC goes low after the conversion is complete, but before the result is written to the ADC Data Registers. This allows a new conversion to be initiated before the current conversion is complete. The new conversion will then start immediately after the current conversion completes. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a "0" to this bit has no effect. 68 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 * Bit 5 - ADFR: ADC Free Run Select When this bit is set (one), the ADC operates in Free Run mode. In this mode, the ADC samples and updates the Data Registers continuously. Clearing this bit (zero) will terminate Free Run mode. * Bit 4 - ADIF: ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the Data Registers are updated. The ADC Conversion Complete interrupt is executed if the ADIE bit and the Ibit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical "1" to the flag. Beware that if doing a Read-Modify-Write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. * Bit 3 - ADIE: ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete interrupt is activated. * Bits 2..0 - ADPS2..ADPS0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 22. ADC Prescaler Selections ADPS2 0 0 0 0 1 1 1 1 ADPS1 0 0 1 1 0 0 1 1 ADPS0 0 1 0 1 0 1 0 1 Division Factor 2 2 4 8 16 32 64 128 ADC Data Register - ADCL AND ADCH Bit $05 ($25) $04 ($26) 15 - ADC7 7 14 - ADC6 6 R R 0 0 13 - ADC5 5 R R 0 0 12 - ADC4 4 R R 0 0 11 - ADC3 3 R R 0 0 10 - ADC2 2 R R 0 0 9 ADC9 ADC1 1 R R 0 0 8 ADC8 ADC0 0 R R 0 0 ADCH ADCL Read/Write R R Initial Value 0 0 When an ADC conversion is complete, the result is found in these two registers. In Free Run mode, it is essential that both registers are read and that ADCL is read before ADCH. 69 1042H-AVR-04/03 Scanning Multiple Channels Since change of analog channel always is delayed until a conversion is finished, the Free Run mode can be used to scan multiple channels without interrupting the converter. Typically, the ADC Conversion Complete interrupt will be used to perform the channel shift. However, the user should take the following fact into consideration: The interrupt triggers once the result is ready to be read. In Free Run mode, the next conversion will start immediately when the interrupt triggers. If ADMUX is changed after the interrupt triggers, the next conversion has already started and the old setting is used. Digital circuitry inside and outside the AT90S4433 generates EMI, which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. The analog part of the AT90S4433 and all analog components in the application should have a separate analog ground plane on the PCB. This ground plane is connected to the digital ground plane via a single point on the PCB. 2. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane and keep them well away from high-speed switching digital tracks. 3. The AVCC pin on the AT90S4433 should be connected to the digital VCC supply voltage via an LC network as shown in Figure 49. 4. Use the ADC Noise Canceler function to reduce induced noise from the CPU. 5. If some Port C pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. Figure 49. ADC Power Connections VCC ADC Noise Canceling Techniques 28 27 26 25 24 23 AT90S4433 22 21 20 19 PC5 (ADC5) PC4 (ADC4) PC3 (ADC3) PC2 (ADC2) PC1 (ADC1) Analog Ground Plane 100 nF AGND AREF AVCC PB5 Note that since AVCC feeds the Port C output drivers, the RC network shown should not be employed if any Port C serve as outputs. 70 AT90S/LS4433 1042H-AVR-04/03 10 H PC0 (ADC0) AT90S/LS4433 ADC Characteristics TA = -40C to 85C Symbol Parameter Resolution Absolute Accuracy Absolute Accuracy Absolute Accuracy Integral Non-linearity Differential Non-linearity Zero Error (Offset) Conversion Time Clock Frequency AVCC VREF RREF RAIN Notes: Analog Supply Voltage Reference Voltage Reference Input Resistance Analog Input Resistance 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 6.0V. 65 50 VCC - 0.3 2 6 10 100 (1) Condition Min Typ 10 Max Units Bits VREF = 4V ADC clock = 200 kHz VREF = 4V ADC clock = 1 MHz VREF = 4V ADC clock = 2 MHz VREF > 2V VREF > 2V 1 4 16 0.5 0.5 1 2 LSB LSB LSB LSB LSB LSB 260 200 VCC + 0.3 AVCC 13 (2) s kHz V V k M 71 1042H-AVR-04/03 I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Port B is a 6-bit bi-directional I/O port. Three I/O memory address locations are allocated for the Port B, one each for the Data Register - PORTB, $18($38), Data Direction Register - DDRB, $17($37), and the Port B Input Pins - PINB, $16($36). The Port B Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pull-up resistors. The Port B output buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port B pins with alternate functions are shown in Table 23. Table 23. Port B Pin Alternate Functions Port Pin PB0 PB1 PB2 PB3 PB4 PB5 Alternate Functions ICP (Timer/Counter1 Input Capture Pin) OC1 (Timer/Counter1 Output Compare Match Output) SS (SPI Slave Select Input) MOSI (SPI Bus Master Output/Slave Input) MISO (SPI Bus Master Input/Slave Output) SCK (SPI Bus Serial Clock) Port B When the pins are used for the alternate function, the DDRB and PORTB Registers have to be set according to the alternate function description. Port B Data Register - PORTB Bit $18 ($38) Read/Write Initial Value 7 - 6 - 5 PORTB5 4 PORTB4 3 PORTB3 2 PORTB2 1 PORTB1 0 PORTB0 PORTB R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Port B Data Direction Register - DDRB Bit $17 ($37) Read/Write Initial Value 7 - R 0 6 - R 0 5 DDB5 R/W 0 4 DDB4 R/W 0 3 DDB3 R/W 0 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB Port B Input Pins Address - PINB Bit $16 ($36) Read/Write Initial Value 7 - R 0 6 - R 0 5 PINB5 R N/A 4 PINB4 R N/A 3 PINB3 R N/A 2 PINB2 R N/A 1 PINB1 R N/A 0 PINB0 R N/A PINB 72 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 The Port B Input Pins address (PINB) is not a register; this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. Port B as General Digital I/O All six pins in Port B have equal functionality when used as digital I/O pins. PBn, general I/O pin: The DDBn bit in the DDRB Register selects the direction of this pin. If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) when the pin is configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 24. DDBn Effects on Port B Pins(1) DDBn 0 0 1 1 Note: PORTBn 0 1 0 1 I/O Input Input Output Output Pull-up No Yes No No Comment Tri-state (high-Z) PBn will source current if ext. pulled low. Push-pull Zero Output Push-pull One Output 1. n: 5..0, pin number. Alternate Functions of Port B The alternate pin configuration is as follows: * SCK - Port B, Bit 5 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input, regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the description of the SPI port for further details. * MISO - Port B, Bit 4 MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a Master, this pin is configured as an input, regardless of the setting of DDB4. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit. See the description of the SPI port for further details. * MOSI - Port B, Bit 3 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input, regardless of the setting of DDB3. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit. See the description of the SPI port for further details. * SS - Port B, Bit 2 SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an input, regardless of the setting of DDB2. As a Slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a Master, the data direction of this pin is 73 1042H-AVR-04/03 controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit. See the description of the SPI port for further details. * OC1 - Port B, Bit 1 OC1, Output Compare Match output: PB1 pin can serve as an external output for the Timer/Counter1 Output Compare. The pin has to be configured as an output (DDB1 set [one]) to serve this function. See the timer description on how to enable this function. The OC1 pin is also the output pin for the PWM mode timer function. * ICP - Port B, Bit 0 ICP, Input Capture Pin: PB0 pin can serve as an external input for the Timer/Counter1 input capture. The pin has to be configured as an input (DDB0 cleared [zero]) to serve this function. See the timer description on how to enable this function. Figure 50. Port B Schematic Diagram (Pin PB0) RD MOS PULLUP RESET R Q D DDB6 C RESET R Q D PORTB0 C RL PB0 WP RP WP: WD: RL: RP: RD: ACIC: ACO: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB COMPARATOR IC ENABLE COMPARATOR OUTPUT 0 NOISE CANCELER 1 ICNC1 ICES1 ACIC ACO EDGE SELECT ICF1 74 AT90S/LS4433 1042H-AVR-04/03 DATA BUS WD AT90S/LS4433 Figure 51. Port B Schematic Diagram (Pin PB1) DDB1 PB1 PORTB1 WP: WD: RL: RP: RD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB Figure 52. Port B Schematic Diagram (Pin PB2) RD MOS PULLUP RESET Q D DDB2 C RESET PB2 Q D PORTB2 C RL WP RP WP: WD: RL: RP: RD: MSTR: SPE: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI MASTER ENABLE SPI ENABLE MSTR SPE SPI SS DATA BUS WD 75 1042H-AVR-04/03 Figure 53. Port B Schematic Diagram (Pin PB3) RD MOS PULLUP RESET R Q D DDB3 C RESET R Q D PORTB3 C RL PB3 WP RP WP: WD: RL: RP: RD: SPE: MSTR WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT MSTR SPE SPI MASTER OUT SPI SLAVE IN Figure 54. Port B Schematic Diagram (Pin PB4) RD MOS PULLUP RESET R Q D DDB4 C RESET R Q D PORTB4 C RL PB4 WP RP WP: WD: RL: RP: RD: SPE: MSTR WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT MSTR SPE SPI SLAVE OUT SPI MASTER IN 76 AT90S/LS4433 1042H-AVR-04/03 DATA BUS WD DATA BUS WD AT90S/LS4433 Figure 55. Port B Schematic Diagram (Pin PB5) RD MOS PULLUP RESET R Q D DDB5 C RESET R Q D PORTB5 C RL PB5 WP RP WP: WD: RL: RP: RD: SPE: MSTR WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT MSTR SPE SPI CLOCK OUT SPI CLOCK IN Port C Port C is a 6-bit bi-directional I/O port. Three I/O memory address locations are allocated for the Port C, one each for the Data Register - PORTC, $15($35), Data Direction Register - DDRC, $14($34), and the Port C Input Pins - PINC, $13($33). The Port C Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pull-up resistors. The Port C output buffers can sink 20 mA and thus drive LED displays directly. When pins PC0 to PC5 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. Port C has an alternate function as analog inputs for the ADC. If some Port C pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This might corrupt the result of the conversion. During Power-down mode, the Schmitt triggers of the digital inputs are disconnected. This allows an analog voltage close to VCC/2 to be present during Power-down without causing excessive power consumption. DATA BUS WD 77 1042H-AVR-04/03 Port C Data Register - PORTC Bit $15 ($35) Read/Write Initial Value 7 - 6 - 5 PORTC5 4 PORTC4 3 PORTC3 2 PORTC2 1 PORTC1 0 PORTC0 PORTC R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Port C Data Direction Register - DDRC Bit $14 ($34) Read/Write Initial Value 7 - R 0 6 - R 0 5 DDC5 R/W 0 4 DDC4 R/W 0 3 DDC3 R/W 0 2 DDC2 R/W 0 1 DDC1 R/W 0 0 DDC0 R/W 0 DDRC Port C Input Pins Address - PINC Bit $13 ($33) Read/Write Initial Value 7 - R 0 6 - R 0 5 PINC5 R N/A 4 PINC4 R N/A 3 PINC3 R N/A 2 PINC2 R N/A 1 PINC1 R N/A 0 PINC0 R N/A PINC The Port C Input Pins address (PINC) is not a register; this address enables access to the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the pins are read. Port C as General Digital I/O All six pins in Port C have equal functionality when used as digital I/O pins. PCn, general I/O pin: The DDCn bit in the DDRC Register selects the direction of this pin. If DDCn is set (one), PCn is configured as an output pin. If DDCn is cleared (zero), PCn is configured as an input pin. If PORTCn is set (one) when the pin is configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, PORTCn has to be cleared (zero) or the pin has to be configured as an output pin.The port pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 25. DDCn Effects on Port C Pins(1) DDCn 0 0 1 1 Note: PORTCn 0 1 0 1 I/O Input Input Output Output Pull-up No Yes No No Comment Tri-state (high-Z) PCn will source current if ext. pulled low. Push-pull Zero Output Push-pull One Output 1. n: 5..0, pin number 78 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Port C Schematics Note that all port pins are synchronized. The synchronization latch is, however, not shown in the figure. Figure 56. Port C Schematic Diagrams (Pins PC0 - PC5) RD MOS PULLUP RESET Q D DDCn C RESET PCn Q D PORTCn C RL WP PWRDN RP TO ADC MUX WP: WD: RL: RP: RD: PWRDN: n: WRITE PORTC WRITE DDRC READ PORTC LATCH READ PORTC PIN READ DDRC POWER DOWN MODE 0-5 ADCn DATA BUS WD 79 1042H-AVR-04/03 Port D Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for Port D, one each for the Data Register - PORTD, $12($32), Data Direction Register - DDRD, $11($31), and the Port D Input Pins - PIND, $10($30). The Port D Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Some Port D pins have alternate functions as shown in Table 26. Table 26. Port D Pin Alternate Functions Port Pin PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Alternate Function RXD (UART Input Line) TXD (UART Output Line) INT0 (External Interrupt 0 Input) INT1 (External Interrupt 1 Input) T0 (Timer/Counter 0 External Counter Input) T1 (Timer/Counter 1 External Counter Input) AIN0 (Analog Comparator Positive Input) AIN1 (Analog Comparator Negative Input) Port D Data Register - PORTD Bit $12 ($32) Read/Write Initial Value 7 PORTD7 6 PORTD6 5 PORTD5 4 PORTD4 3 PORTD3 2 PORTD2 1 PORTD1 0 PORTD0 PORTD R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Port D Data Direction Register - DDRD Bit $11 ($31) Read/Write Initial Value 7 DDD7 R/W 0 6 DDD6 R/W 0 5 DDD5 R/W 0 4 DDD4 R/W 0 3 DDD3 R/W 0 2 DDD2 R/W 0 1 DDD1 R/W 0 0 DDD0 R/W 0 DDRD Port D Input Pins Address - PIND Bit $10 ($30) Read/Write Initial Value 7 PIND7 R N/A 6 PIND6 R N/A 5 PIND5 R N/A 4 PIND4 R N/A 3 PIND3 R N/A 2 PIND2 R N/A 1 PIND1 R N/A 0 PIND0 R N/A PIND The Port D Input Pins address (PIND) is not a register; this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read. 80 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Port D as General Digital I/O PDn, General I/O pin: The DDDn bit in the DDRD Register selects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PDn is set (one) when configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the PDn has to be cleared (zero) or the pin has to be configured as an output pin.The port pins are tristated when a reset condition becomes active, even if the clock is not running. Table 27. DDDn Bits on Port D Pins(1) DDDn 0 0 1 1 Note: PORTDn 0 1 0 1 I/O Input Input Output Output Pull-up No Yes No No Comment Tri-state (high-Z) PDn will source current if ext. pulled low. Push-pull Zero Output Push-pull One Output 1. n: 7,6..0, pin number. Alternate Functions of Port D * AIN1 - Port D, Bit 7 AIN1, Analog Comparator Negative Input. When configured as an input (DDD7 is cleared [zero]), and with the internal MOS pull-up resistor switched off (PD7 is cleared [zero]), this pin also serves as the negative input of the On-chip Analog Comparator. During Power-down mode, the Schmitt trigger of the digital input is disconnected. This allows analog signals, which are close to VCC/2, to be present during Power-down without causing excessive power consumption. * AIN0 - Port D, Bit 6 AIN0, Analog Comparator Positive Input. When configured as an input (DDD6 is cleared [zero]), and with the internal MOS pull-up resistor switched off (PD6 is cleared [zero]), this pin also serves as the positive input of the On-chip Analog Comparator. During Power-down mode, the Schmitt trigger of the digital input is disconnected. This allows analog signals, which are close to VCC/2, to be present during Power-down without causing excessive power consumption. * T1 - Port D, Bit 5 T1, Timer/Counter1 Counter Source. See the Timer description for further details * T0 - Port D, Bit 4 T0: Timer/Counter0 Counter Source. See the Timer description for further details. * INT1 - Port D, Bit 3 INT1, External Interrupt Source 1: The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source. * INT0 - Port D, Bit 2 INT0, External Interrupt Source 0: The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source. 81 1042H-AVR-04/03 * TXD - Port D, Bit 1 Transmit Data (Data Output pin for the UART). When the UART Transmitter is enabled, this pin is configured as an output, regardless of the value of DDD1. * RXD - Port D, Bit 0 Receive Data (Data Input pin for the UART). When the UART Receiver is enabled, this pin is configured as an input, regardless of the value of DDD0. When the UART forces this pin to be an input, a logical "1" in PORTD0 will turn on the internal pull-up. Port D Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 57. Port D Schematic Diagram (Pin PD0) RD MOS PULLUP RESET Q D DDD0 C RESET PD0 Q D PORTD0 C RL WP RP WP: WD: RL: RP: RD: RXD: RXEN: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART RECEIVE DATA UART RECEIVE ENABLE RXEN RXD 82 AT90S/LS4433 1042H-AVR-04/03 DATA BUS WD AT90S/LS4433 Figure 58. Port D Schematic Diagram (Pin PD1) RD MOS PULLUP RESET R Q D DDD1 C RESET R Q D PORTD1 C RL PD1 WP RP WP: WD: RL: RP: RD: TXD: TXEN: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART TRANSMIT DATA UART TRANSMIT ENABLE TXEN TXD Figure 59. Port D Schematic Diagram (Pins PD2 and PD3) DATA BUS WD 83 1042H-AVR-04/03 Figure 60. Port D Schematic Diagram (Pins PD4 and PD5) DDDn PDn PORTBn WP: WD: RL: RP: RD: n: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD 4, 5 2 Figure 61. Port D Schematic Diagram (Pins PD6 and PD7) RD MOS PULLUP RESET Q D DDDn C RESET PDn Q D PORTDn C RL WP PWRDN RP TO COMPARATOR WP: WD: RL: RP: RD: PWRDN: n: m: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD POWER DOWN MODE 6, 7 0, 1 AINm 84 AT90S/LS4433 1042H-AVR-04/03 DATA BUS WD AT90S/LS4433 Memory Programming Program and Data Memory Lock Bits The AT90S4433 MCU provides two Lock bits, which can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional features listed in Table 28. The Lock bits can only be erased with the Chip Erase command. Table 28. Lock Bit Protection Modes Memory Lock Bits Mode 1 2 3 Note: LB1 1 0 0 LB2 1 1 0 Protection Type No memory lock features enabled. Further programming of the Flash and EEPROM is disabled.(1) Same as mode 2, and verify is also disabled. 1. In Parallel mode, programming of the Fuse bits are also disabled. Program the Fuse bits before programming the Lock bits. Fuse Bits The AT90S4433 has six Fuse bits, SPIEN, BODLEVEL, BODEN and CKSEL2..0. * When the SPIEN Fuse is programmed ("0"), Serial Program and Data Downloading is enabled. Default value is programmed ("0"). This bit is not accessible in Serial Programming mode. The BODLEVEL Fuse selects the Brown-out Detection Level and changes the startup times. See "Brown-out Detection" on page 25. Default value is unprogrammed ("1"). When the BODEN Fuse is programmed ("0"), the Brown-out Detector is enabled. See "Brown-out Detection" on page 25. Default value is unprogrammed ("1"). CKSEL2..0: See Table 5 on page 23 for which combination of CKSEL2..0 to use. Default value is "010". * * * Signature Bytes All Atmel microcontrollers have a 3-byte signature code that identifies the device. This code can be read in both serial and parallel mode. The three bytes reside in a separate address space. For the AT90S4433(1) they are: 1. $000: $1E (indicates manufactured by Atmel) 2. $001: $92 (indicates 4 KB Flash memory) 3. $002: $03 (indicates AT90S4433 device when signature byte $001 is $92) Note: 1. When both Lock bits are programmed (Lock mode 3), the signature bytes cannot be read in Serial mode. Reading the signature bytes will return $00, $01 and $02. 85 1042H-AVR-04/03 Programming the Flash and EEPROM Atmel's AT90S4433 offers 4K bytes of In-System Reprogrammable Flash Program memory and 256 bytes of EEPROM Data memory. The AT90S4433 is shipped with the On-chip Flash Program and EEPROM Data memory arrays in the erased state (i.e., contents = $FF) and ready to be programmed. This device supports a High-voltage (12V) Parallel Programming mode and a Low-voltage Serial Programming mode. The +12V is used for programming enable only, and no current of significance is drawn by this pin. The Serial Programming mode provides a convenient way to download program and data into the AT90S4433 inside the user's system. The Program and Data memory arrays on the AT90S4433 are programmed byte-bybyte in either Programming mode. For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction in the Serial Programming mode. During programming, the supply voltage must be in accordance with Table 29. Table 29. Supply Voltage during Programming Part AT90LS4433 AT90S4433 Serial Programming 2.7 - 6.0V 4.0 - 6.0V Parallel Programming 4.5 - 5.5V 4.5 - 5.5V Parallel Programming Signal Names This section describes how to Parallel program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the AT90S4433. In this section, some pins of the AT90S4433 are referenced by signal names describing their function during Parallel programming. See Figure 62 and Table 30. Pins not described in Table 30 are referenced by pin name. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit codings are shown in Table 31. When pulsing WR or OE, the command loaded determines the action executed. The command is a byte where the different bits are assigned functions as shown in Table 32. Figure 62. Parallel Programming AT90S4433 RDY/BSY OE WR BS XA0 XA1 +12V PD1 PD2 PD3 PD4 PD5 PD6 RESET VCC PC1 - PC0, PB5 - PB0 +5V DATA XTAL1 GND 86 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Table 30. Pin Name Mapping Signal Name in Programming Mode RDY/BSY OE WR BS XA0 XA1 DATA Pin Name PD1 PD2 PD3 PD4 PD5 PD6 PC1 - 0, PB5 - 0 I/O O I I I I I I/O Function 0: Device is busy programming, 1: Device is ready for new command Output Enable (active low) Write Pulse (active low) Byte Select ("0" selects Low Byte, "1" selects High Byte) XTAL Action Bit 0 XTAL Action Bit 1 Bi-directional Data Bus (output when OE is low) Table 31. XA1 and XA0 Coding XA1 0 0 1 1 XA0 0 1 0 1 Action when XTAL1 is Pulsed Load Flash or EEPROM Address (high or low address byte determined by BS) Load Data (high or low data byte for Flash determined by BS) Load Command No Action, Idle Table 32. Command Byte Bit Coding Command Byte 1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 Command Executed Chip Erase Write Fuse Bits Write Lock Bits Write Flash Write EEPROM Read Signature Bytes Read Fuse and Lock Bits Read Flash Read EEPROM Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply supply voltage according to Table 29, between VCC and GND. 2. Set the RESET and BS pin to "0" and wait at least 100 ns. 3. Apply 11.5 - 12.5V to RESET. Any activity on BS within 100 ns after +12V has been applied to RESET will cause the device to fail entering Programming mode. 87 1042H-AVR-04/03 Chip Erase The Chip Erase command will erase the Flash and EEPROM memories and the Lock bits. The Lock bits are not reset until the Flash and EEPROM have been completely erased. The Fuse bits are not changed. Chip Erase must be performed before the Flash or EEPROM is reprogrammed. A: Load Command "Chip Erase" 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS to "0". 3. Set DATA to "1000 0000". This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a tWLWH_CE wide negative pulse to execute Chip Erase. See Table 33 for tWLWH_CE value. Chip Erase does not generate any activity on the RDY/BSY pin. Programming the Flash A: Load Command "Write Flash" 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS to "0". 3. Set DATA to "0001 0000". This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. B: Load Address High Byte 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS to "1". This selects High Byte. 3. Set DATA = Address High Byte ($00 - $07). 4. Give XTAL1 a positive pulse. This loads the address High Byte. C: Load Address Low Byte 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS to "0". This selects Low Byte. 3. Set DATA = Address Low Byte ($00 - $FF). 4. Give XTAL1 a positive pulse. This loads the address Low Byte. D: Load Data Low Byte 1. Set XA1, XA0 to "01". This enables data loading. 2. Set DATA = Data Low Byte ($00 - $FF). 3. Give XTAL1 a positive pulse. This loads the data Low Byte. E: Write Data Low Byte 1. Set BS to "0". This selects low data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. (See Figure 63 for signal waveforms.) F: Load Data High Byte 1. Set XA1, XA0 to "01". This enables data loading. 2. Set DATA = Data High Byte ($00 - $FF). 3. Give XTAL1 a positive pulse. This loads the data High Byte. 88 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 G: Write Data High Byte 1. Set BS to "1". This selects high data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. (See Figure 64 for signal waveforms.) The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered: * * * The command needs to be loaded only once when writing or reading multiple memory locations. Address High Byte needs to be loaded only before programming a new 256-word page in the Flash. Skip writing the data value $FF, that is, the contents of the entire Flash and EEPROM after a Chip Erase. These considerations also apply to EEPROM programming and Flash, EEPROM and signature bytes reading. Figure 63. Programming the Flash Waveforms DATA $10 ADDR. HIGH ADDR. LOW DATA LOW XA1 XA0 BS XTAL1 WR RDY/BSY RESET OE 12V 89 1042H-AVR-04/03 Figure 64. Programming the Flash Waveforms (Continued) DATA DATA HIGH XA1 XA0 BS XTAL1 WR RDY/BSY RESET OE +12V Reading the Flash The algorithm for reading the Flash memory is as follows (refer to "Programming the Flash" for details on command and address loading): A: Load Command "0000 0010". B: Load Address High Byte ($00 - $07). C: Load Address Low Byte ($00 - $FF). 1. Set OE to "0", and BS to "0". The Flash word Low Byte can now be read at DATA. 2. Set BS to "1". The Flash word High Byte can now be read from DATA. 3. Set OE to "1". Programming the EEPROM The programming algorithm for the EEPROM Data memory is as follows (refer to "Programming the Flash" for details on command, address and data loading): A: Load Command "0001 0001". B: Load Address Low Byte ($00 - $FF). C: Load Data Low Byte ($00 - $FF). D: Write Data Low Byte. Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to "Programming the Flash" for details on command and address loading): A: Load Command "0000 0011". B: Load Address Low Byte ($00 - $FF). 1. Set OE to "0", and BS to "0". The EEPROM data byte can now be read at DATA. 2. Set OE to "1". 90 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Programming the Fuse Bits The algorithm for programming the Fuse bits is as follows (refer to "Programming the Flash" for details on command and data loading): A: Load Command "0100 0000". B: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. Bit 5 = SPIEN Fuse bit Bit 4 = BODLEVEL Fuse bit Bit 3 = BODEN Fuse bit Bit 2 = CKSEL2 Fuse bit Bit 1 = CKSEL1 Fuse bit Bit 0 = CKSEL0 Fuse bit Bits 7 - 6 = "1". These bits are reserved and should be left unprogrammed ("1"). 1. Give WR a tWLWH_PFB wide negative pulse to execute the programming, tWLWH_PFB is found in Table 33. Programming the Fuse bits does not generate any activity on the RDY/BSY pin. Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to "Programming the Flash" for details on command and data loading): A: Load Command "0010 0000". B: Load Data Low Byte. Bit n = "0" programs the Lock bit. Bit 2 = Lock bit 2 Bit 1 = Lock bit 1 Bits 7 - 3, 0 = "1". These bits are reserved and should be left unprogrammed ("1"). C: Write Data Low Byte. The Lock bits can only be cleared by executing Chip Erase. Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to "Programming the Flash" for details on command loading): A: Load Command "0000 0100". 1. Set OE to "0", and BS to "0". The status of the Fuse bits can now be read at DATA ("0" means programmed). Bit 5 = SPIEN Fuse bit Bit 4 = BODLEVEL Fuse bit Bit 3 = BODEN Fuse bit Bit 2 = CKSEL2 Fuse bit Bit 1 = CKSEL1 Fuse bit Bit 0 = CKSEL0 Fuse bit 2. Set BS to "1". The status of the Lock bits can now be read at DATA ("0" means programmed). Bit 2 = Lock Bit 2 Bit 1= Lock Bit 1 3. Set OE to "1". 91 1042H-AVR-04/03 Reading the Signature Bytes The algorithm for reading the signature bytes is as follows (refer to "Programming the Flash" for details on command and address loading): A: Load Command "0000 1000". B: Load Address Low Byte ($00 - $02). 1. Set OE to "0", and BS to "0". The selected signature byte can now be read at DATA. 2. Set OE to "1". Parallel Programming Characteristics Figure 65. Parallel Programming Timing tXLWL XTAL1 tDVXH Data & Contol (DATA, XA0/1, BS) WR RDY/BSY tWLRH tOLDV tRHBX tXHXL tXLDX tBVWL tWHRL DATA Table 33. Parallel Programming Characteristics TA = 25C 10%, VCC = 5V 10% Symbol VPP IPP tDVXH tXHXL tXLDX tXLWL tBVWL tRHBX tWLWH tWHRL tWLRH tXLOL tOLDV tOHDZ tWLWH_CE tWLWH_PFB Notes: Parameter Programming Enable Voltage Programming Enable Current Data and Control Setup before XTAL1 High XTAL1 Pulse Width High Data and Control Hold after XTAL1 Low XTAL1 Low to WR Low BS Valid to WR Low BS Hold after RDY/BSY High WR Pulse Width Low(1) WR High to RDY/BSY Low WR Low to RDY/BSY High XTAL1 Low to OE Low OE Low to DATA Valid OE High to DATA Tri-stated WR Pulse Width Low for Chip Erase WR Pulse Width Low for Programming the Fuse Bits 5.0 1.0 10.0 1.5 (2) (2) Min 11.5 Typ Max 12.5 250.0 Units V A ns ns ns ns ns ns ns 67.0 67.0 67.0 67.0 67.0 67.0 67.0 20.0 0.5 67.0 20.0 20.0 15.0 1.8 0.7 0.9 ns ms ns ns ns ms ms 1. Use tWLWH_CE for Chip Erase and tWLWH_PFB for programming the Fuse bits. 2. If tWLWH is held longer than tWLRH, no RDY/BSY pulse will be seen. 92 AT90S/LS4433 1042H-AVR-04/03 Read OE tXLOL tOHDZ Write tWLWH AT90S/LS4433 Serial Downloading Both the Program and Data memory arrays can be programmed using the SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output) (see Figure 66). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase instructions can be executed. Figure 66. Serial Programming and Verify AT90S/LS4433 VCC 4.0 - 6.0 V (AT90S4433) 2.7 - 6.0 V (AT90LS4433) DATA OUT INSTR. IN CLOCK IN PB4(MISO) PB3(MOSI) PB5(SCK) GND CLOCK INPUT RESET XTAL1 GND For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first execute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the program and EEPROM arrays into $FF. The Program and EEPROM memory arrays have separate address spaces: 0000 to $07FF for Program memory and $0000 to $00FF for EEPROM memory. Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 XTAL1 clock cycles High: > 2 XTAL1 clock cycles Serial Programming Algorithm When writing serial data to the AT90S4433, data is clocked on the rising edge of CLK. When reading data from the AT90S4433, data is clocked on the falling edge of CLK. See Figure 67, Figure 68 and Table 36 for details. To program and verify the AT90S4433 in the Serial Programming mode, the following sequence is recommended (see 4-byte instruction formats in Table 35): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". If a crystal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is held low during Power-up. In this case, RESET must be given a positive pulse of at least two XTAL1 cycles' duration after SCK has been set to "0". 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI/PB3. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the second byte ($53) will echo back when issu93 1042H-AVR-04/03 ing the third byte of the Programming Enable instruction. Whether or not the echo is correct, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is no functional device connected. 4. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE after the instruction, give RESET a positive pulse, and start over from step 2. See Table 37 on page 97 for tWD_ERASE value. 5. The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. Use data polling to detect when the next byte in the Flash or EEPROM can be written. If polling is not used, wait tWD_PROG before transmitting the next instruction. In an erased device, no $FFs in the data file(s) need to be programmed. See Table 38 on page 97 for tWD_PROG value. 6. Any memory location can be verified by using the Read instruction, which returns the content at the selected address at serial output MISO/PB4. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set XTAL1 to "0" (if a crystal is not used). Set RESET to "1". Turn VCC power off. Data Polling EEPROM When a byte is being programmed into the EEPROM, reading the address location being programmed will give the value P1 until the auto-erase is finished, and then the value P2. See Table 34 for P1 and P2 values. At the time the device is ready for a new EEPROM byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the values P1 and P2, so when programming these values, the user will have to wait for at least the prescribed time tWD_PROG before programming the next byte. See Table 38 for tWD_PROG value. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. This does not apply if the EEPROM is reprogrammed without first Chip Erasing the device. Table 34. Read Back Value during EEPROM Polling Part AT90S/LS4433 P1 $00 P2 $FF 94 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Data Polling Flash When a byte is being programmed into the Flash, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $FF, so when programming this value, the user will have to wait for at least tWD_PROG before programming the next byte. As a chiperased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. Figure 67. Serial Programming Waveforms SERIAL DATA INPUT PB3(MOSI) SERIAL DATA OUTPUT PB4(MISO) SERIAL CLOCK INPUT PB5(SCK) MSB LSB MSB LSB 95 1042H-AVR-04/03 Table 35. Serial Programming Instruction Set Instruction Format Instruction Programming Enable Chip Erase Byte 1 1010 1100 1010 1100 0010 H000 Read Program Memory 0100 H000 Write Program Memory Read EEPROM Memory Write EEPROM Memory Write Lock Bits Read Lock Bits Read Sigature Bytes Write Fuse Bits Read Fuse Bits Note: 1010 0000 1100 0000 1010 1100 0101 1000 0011 0000 1010 1100 0101 0000 xxxx xxxx xxxx xxxx 1111 1211 xxxx xxxx xxxx xxxx 1017 6543 xxxx xxxx bbbb bbbb bbbb bbbb xxxx xxxx xxxx xxxx xxxx xxbb xxxx xxxx xxxx xxxx oooo oooo iiii iiii xxxx xxxx xxxx x21x oooo oooo xxxx xxxx xx87 6543 xxxx xaaa bbbb bbbb iiii iiii Byte 2 0101 0011 100x xxxx xxxx xaaa Byte 3 xxxx xxxx xxxx xxxx bbbb bbbb Byte4 xxxx xxxx xxxx xxxx oooo oooo Operation Enable Serial Programming while RESET is low. Chip Erase Flash and EEPROM memory arrays. Read H (high or low) data o from program memory at word address a:b. Write H (high or low) data i to program memory at word address a:b. Read data o from EEPROM memory at address a:b. Write data i to EEPROM memory at address a:b. Write Lock bits. Set bits 1,2= "0" to program Lock bits. Read Lock bits. "0" = programmed, "1" = unprogrammed. Read signature byte o at address b.(1) Set bits 7 - 3 = "0" to program, "1" to unprogram. Read Fuse bits. "0" = programmed, "1" = unprogrammed. 1. The signature bytes are not readable in lock mode 3, i.e., both Lock bits programmed. a = address high bits b = address low bits H = 0 - Low Byte, 1 - High Byte o = data out i = data in x = don't care 1 = Lock bit 1 2 = Lock bit 2 3 = CKSEL0 Fuse 4 = CKSEL1 Fuse 5 = CKSEL2 Fuse 6 = BODEN Fuse 7 = BODLEVEL Fuse 8 = SPIEN Fuse 96 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Serial Programming Characteristics Figure 68. Serial Programming Timing MOSI tOVSH SCK MISO tSLIV tSHSL tSHOX tSLSH Table 36. Serial Programming Characteristics, TA = -40C to 85C, VCC = 2.7 - 6.0V (unless otherwise noted) Symbol 1/tCLCL tCLCL 1/tCLCL tCLCL tSHSL tSLSH tOVSH tSHOX tSLIV Parameter Oscillator Frequency (VCC = 2.7 - 6.0V) Oscillator Period (VCC = 2.7 - 6.0V) Oscillator Frequency (VCC = 4.0 - 6.0V) Oscillator Period (VCC = 4.0 - 6.0V) SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High MOSI Hold after SCK High SCK Low to MISO Valid Min 0 250 0 125 2 tCLCL 2 tCLCL tCLCL 2 tCLCL 10 16 32 8 Typ Max 4 Units MHz ns MHz ns ns ns ns ns ns Table 37. Minimum Wait Delay after the Chip Erase Instruction Symbol tWD_ERASE 3.2V 18 ms 3.6V 14 ms 4.0V 12 ms 5.0V 8 ms Table 38. Minimum Wait Delay after Writing a Flash or EEPROM Location Symbol tWD_PROG 3.2V 9 ms 3.6V 7 ms 4.0V 6 ms 5.0V 4 ms 97 1042H-AVR-04/03 Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin except RESET with Respect to Ground .............................-1.0V to VCC + 0.5V Voltage on RESET with Respect to Ground ....-1.0V to +13.0V Maximum Operating Voltage ............................................ 6.6V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins ............................... 300.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = -40C to 85C, VCC = 2.7V to 6.0V (unless otherwise noted) Symbol VIL VIL1 VIH VIH1 VIH2 VOL VOH IIL IIH RRST RI/O Parameter Input Low Voltage Input Low Voltage RESET Input High Voltage Input High Voltage Input High Voltage Output Low Voltage(3) (Ports B, C, D) Output High Voltage(4) (Ports B, C, D) Input Leakage Current I/O pin Input Leakage Current I/O pin Reset Pull-up I/O Pin Pull-up Resistor Active 4 MHz, VCC = 3V Idle 4 MHz, VCC = 3V ICC Power Supply Current Power-down, VCC = 3V WDT enabled(5) Power-down, VCC = 3V WDT disabled(5) Except (XTAL, RESET) XTAL RESET IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V IOH = -3 mA, VCC = 5V IOH = -1.5 mA, VCC = 3V VCC = 6V, pin = low (absolute value) VCC = 6V, pin = high (absolute value) 100.0 35.0 4.3 2.2 8.0 8.0 500.0 120.0 5.0 2.0 20.0 10.0 0.7 VCC(2) 0.7 VCC (2) (2) Condition Except (XTAL, RESET) XTAL Min -0.5 -0.5 Typ Max 0.3 VCC (1) Units V V V V V V V A A k k mA mA A A 0.2 VCC(1) VCC + 0.5 VCC + 0.5 VCC + 0.5 0.6 0.5 0.85 VCC 98 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 DC Characteristics (Continued) TA = -40C to 85C, VCC = 2.7V to 6.0V (unless otherwise noted) Symbol VACIO IACLK tACPD Notes: Parameter Analog Comparator Input Offset Voltage Analog Comparator Input Leakage A Analog Comparator Propagation Delay Condition VCC = 5.0V Vin = VCC/2 VCC = 5.0V Vin = VCC/2 VCC = 2.7V VCC = 4.0V -50.0 750.0 500.0 Min Typ Max 40.0 50.0 Units mV nA ns 1. "Max" means the highest value where the pin is guaranteed to be read as low (logical "0"). 2. "Min" means the lowest value where the pin is guaranteed to be read as high (logical "1"). 3. Although each I/O port can sink more than the test conditions (20 mA at VCC = 5.0V, 10 mA at VCC = 3.0V) under steadystate conditions (non-transient), the following must be observed: 1] The sum of all IOL, for all ports, should not exceed 300 mA. 2] The sum of all IOL, for ports C0 - C5, should not exceed 100 mA. 3] The sum of all IOL, for ports B0 - B5, D0 - D7 and XTAL2, should not exceed 200 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (3 mA at VCC = 5.0V, 1.5 mA at VCC = 3.0V) under steadystate conditions (non-transient), the following must be observed: 1] The sum of all IOH, for all ports, should not exceed 300 mA. 2] The sum of all IOH, for ports C0 - C5, should not exceed 100 mA. 3] The sum of all IOH, for ports B0 - B5, D0 - D7 and XTAL2, should not exceed 200 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum VCC for Power-down is 2.0V. 99 1042H-AVR-04/03 External Clock Drive Waveforms Figure 69. External Clock VIH1 VIL1 Table 39. External Clock Drive VCC = 2.7V to 6.0V Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Min 0.0 250.0 100.0 100.0 1.6 1.6 Max 4.0 VCC = 4.0V to 6.0V Min 0.0 125.0 50.0 50.0 0.5 0.5 Max 8.0 Units MHz ns ns ns s s 100 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors, such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL * VCC * f, where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. The difference between Power-down mode with Brown-out Detector enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Brown-out Detector. Figure 70. Active Supply Current vs. Frequency ACTIVE SUPPLY CURRENT vs. FREQUENCY TA = 25C 35 VCC = 6V VCC = 5.5V 25 VCC = 5V VCC = 4.5V VCC = 4V VCC = 3.6V VCC = 3.3V 10 5 VCC = 3.0V VCC = 2.7V 30 ICC (mA) 20 15 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Frequency (MHz) 101 1042H-AVR-04/03 Figure 71. Active Supply Current vs. VCC ACTIVE SUPPLY CURRENT vs. VCC FREQUENCY = 4 MHz 14 12 10 TA = 25C TA = 85C ICC (mA) 8 6 4 2 0 2 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 6 Figure 72. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY TA = 25C 18 VCC = 6V 16 14 12 ICC (mA) 10 8 6 4 VCC = 2.7V 2 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VCC = 3.0V VCC = 5.5V VCC = 5V VCC = 4.5V VCC = 4V VCC = 3.6V VCC = 3.3V Frequency (MHz) 102 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Figure 73. Idle Supply Current vs. VCC IDLE SUPPLY CURRENT vs. VCC FREQUENCY = 4 MHz 6 5 TA = 85C 4 ICC (mA) TA = 25C 3 2 1 0 2 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 6 Figure 74. Power-down Supply Current vs. VCC POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 25 TA = 85C 20 15 ICC (A) TA = 70C 10 5 TA = 45C TA = 25C 0 2 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 6 103 1042H-AVR-04/03 Figure 75. Power-down Supply Current vs. VCC POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 120 100 80 ICC (A) TA = 85C TA = 25C 60 40 20 0 2 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 6 Figure 76. Power-down Supply Current vs. VCC POWER-DOWN SUPPLY CURRENT vs. VCC BROWN-OUT DETECTOR ENABLED 140 120 TA = 85C 100 80 60 40 20 0 2 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 6 TA = 25C 104 AT90S/LS4433 1042H-AVR-04/03 ICC (A) AT90S/LS4433 Figure 77. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 0.9 0.8 0.7 0.6 TA = 85C ICC (mA) 0.5 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 6 TA = 25C Analog Comparator offset voltage is measured as absolute offset. Figure 78. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 5V 18 16 14 Offset Voltage (mV) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 TA = 25C TA = 85C Common Mode Voltage (V) 105 1042H-AVR-04/03 Figure 79. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 2.7V 10 TA = 25C 8 Offset Voltage (mV) 6 TA = 85C 4 2 0 0 0.5 1 1.5 Common Mode Voltage (V) 2 2.5 3 Figure 80. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT VCC = 6V TA = 25C 60 50 40 IACLK (nA) 30 20 10 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 6 6.5 7 106 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Figure 81. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 1600 1400 1200 1000 FRC (kHz) TA = 85C TA = 25C 800 600 400 200 0 2 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 6 Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 82. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 5V 120 TA = 25C 100 TA = 85C 80 IOP (A) 60 40 20 0 0 0.5 1 1.5 2 2.5 VOP (V) 3 3.5 4 4.5 5 107 1042H-AVR-04/03 Figure 83. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 30 TA = 25C 25 TA = 85C 20 IOP (A) 15 10 5 0 0 0.5 1 1.5 VOP (V) 2 2.5 3 Figure 84. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 5V 80 70 TA = 25C 60 50 IOL (mA) 40 30 20 10 0 0 0.5 1 1.5 VOL (V) 2 2.5 3 TA = 85C 108 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Figure 85. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 5V 18 16 14 12 TA = 25C TA = 85C IOH (mA) 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOH (V) Figure 86. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 30 TA = 25C 25 20 IOL (mA) TA = 85C 15 10 5 0 0 0.5 1 VOL (V) 1.5 2 109 1042H-AVR-04/03 Figure 87. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 6 TA = 25C 5 4 IOH (mA) TA = 85C 3 2 1 0 0 0.5 1 1.5 VOH (V) 2 2.5 3 Figure 88. I/O Pin Input Threshold Voltage vs. VCC I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC TA = 25C 2.5 2 Threshold Voltage (V) 1.5 1 0.5 0 2.7 4.0 VCC 5.0 110 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Figure 89. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC TA = 25C 0.18 0.16 0.14 Input Hysteresis (V) 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 VCC 5.0 111 1042H-AVR-04/03 Register Summary Address $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22) $01 ($21) $00 ($20) Name SREG Reserved SP Reserved GIMSK GIFR TIMSK TIFR Reserved Reserved MCUCR MCUSR TCCR0 TCNT0 Reserved Reserved TCCR1A TCCR1B TCNT1H TCNT1L OCR1H OCR1L Reserved Reserved ICR1H ICR1L Reserved Reserved Reserved Reserved WDTCR Reserved Reserved EEAR EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRR ACSR ADMUX ADCSR ADCH ADCL UBRRHI Reserved Reserved Reserved Bit 7 I - SP7 INT1 INTF1 TOIE1 TOV1 Bit 6 T - SP6 INT0 INTF0 OCIE1 OCF1 Bit 5 H - SP5 - - - Bit 4 S - SP4 - - - Bit 3 V - SP3 - TICIE1 ICF1 Bit 2 N - SP2 - - - Bit 1 Z - SP1 - TOIE0 TOV0 Bit 0 C - SP0 - - - Page page 19 page 20 page 20 page 27 page 27 page 28 page 29 - - - - - SE - - SM - - ISC11 WDRF - ISC10 BORF CS02 ISC01 EXTRF CS01 ISC00 PORF CS00 page 30 page 26 page 34 page 35 Timer/Counter0 (8 Bits) COM11 ICNC1 COM10 ICES1 - - - - - CTC1 - CS12 PWM11 CS11 PWM10 CS10 page 37 page 38 page 39 page 39 page 40 page 40 Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Output Compare Register High Byte Timer/Counter1 - Output Compare Register Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte page 41 page 41 - - - WDTOE WDE WDP2 WDP1 WDP0 page 43 EEPROM Address Register EEPROM Data Register - - - - EERIE EEMWE EEWE EERE page 45 page 45 page 45 - - - - - - PORTD7 DDD7 PIND7 SPIF SPIE RXC RXCIE ACD - ADEN - ADC7 - - - - - - PORTD6 DDD6 PIND6 WCOL SPE TXC TXCIE AINBG ADCBG ADSC - ADC6 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 - DORD UDRE UDRIE ACO - ADFR - ADC5 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 - MSTR FE RXEN ACI - ADIF - ADC4 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 - CPOL OR TXEN ACIE - ADIE - ADC3 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 - CPHA - CHR9 ACIC MUX2 ADPS2 - ADC2 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 - SPR1 - RXB8 ACIS1 MUX1 ADPS1 ADC9 ADC1 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 - SPR0 - TXB8 ACIS0 MUX0 ADPS0 ADC8 ADC0 page 72 page 72 page 72 page 78 page 78 page 78 page 80 page 80 page 80 page 52 page 52 page 51 page 57 page 57 page 58 page 61 page 62 page 68 page 68 page 69 page 69 page 61 SPI Data Register UART I/O Data Register UART Baud Rate Register UART Baud Rate Register High 112 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the Status Flags are cleared by writing a logical "1" to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. 113 1042H-AVR-04/03 Instruction Set Summary Mnemonic ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID MOV LDI LD LD LD Rd, Rr Rd, Rr Rd, Rr Rd, K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k Rd, Rr Rd, K Rd, X Rd, X+ Rd, -X k Operands Rd, Rr Rd, Rr Rdl, K Rd, Rr Rd, K Rd, Rr Rd, K Rdl, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd, K Rd, K Rd Rd Rd Rd Rd k Description Add Two Registers Add with Carry Two Registers Add Immediate to Word Subtract Two Registers Subtract Constant from Register Subtract with Carry Two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less than Zero, Signed Branch if Half-carry Flag Set Branch if Half-carry Flag Cleared Branch if T-flag Set Branch if T-flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Move between Registers Load Immediate Load Indirect Load Indirect and Post-inc. Load Indirect and Pre-dec. Operation Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b) = 0) PC PC + 2 or 3 if (Rr(b) = 1) PC PC + 2 or 3 if (P(b) = 0) PC PC + 2 or 3 if (P(b) = 1) PC PC + 2 or 3 if (SREG(s) = 1) then PC PC + k + 1 if (SREG(s) = 0) then PC PC + k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V = 0) then PC PC + k + 1 if (N V = 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if (I = 1) then PC PC + k + 1 if (I = 0) then PC PC + k + 1 Rd Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z,N,V,C,H Z,N,V,C,H Z,N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None # Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1 1 2 2 2 ARITHMETIC AND LOGIC INSTRUCTIONS BRANCH INSTRUCTIONS DATA TRANSFER INSTRUCTIONS 114 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Instruction Set Summary (Continued) Mnemonic LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR Rd, P P, Rr Rr Rd P, b P, b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Operands Rd, Y Rd, Y+ Rd, -Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr -X, Rr Y, Rr Y+, Rr -Y, Rr Y+q, Rr Z, Rr Z+, Rr -Z, Rr Z+q, Rr k, Rr Description Load Indirect Load Indirect and Post-inc. Load Indirect and Pre-dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-inc. Load Indirect and Pre-dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-inc. Store Indirect and Pre-dec. Store Indirect Store Indirect and Post-inc. Store Indirect and Pre-dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-inc. Store Indirect and Pre-dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left through Carry Rotate Right through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit Load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Two's Complement Overflow Clear Two's Complement Overflow Set T in SREG Clear T in SREG Set Half-carry Flag in SREG Clear Half-carry Flag in SREG No Operation Sleep Watchdog Reset Operation Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z + 1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0) C, Rd(n+1) Rd(n), C Rd(7) Rd(7) C, Rd(n) Rd(n+1), C Rd(0) Rd(n) Rd(n+1), n = 0..6 Rd(3..0) Rd(7..4), Rd(7..4) Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 (see specific descr. for Sleep function) (see specific descr. for WDR/timer) Flags None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None # Clocks 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT AND BIT-TEST INSTRUCTIONS 115 1042H-AVR-04/03 Ordering Information Power Supply 2.7 - 6.0V Speed (MHz) 4 Ordering Code AT90LS4433-4AC AT90LS4433-4PC AT90LS4433-4AI AT90LS4433-4PI 4.0 - 6.0V 8 AT90S4433-8AC AT90S4433-8PC AT90S4433-8AI AT90S4433-8PI Package 32A 28P3 32A 28P3 32A 28P3 32A 28P3 Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Package Type 32A 28P3 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 116 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Packaging Information 32A PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0~7 A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 8.75 6.90 8.75 6.90 0.30 0.09 0.45 NOM - - 1.00 9.00 7.00 9.00 7.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 9.25 7.10 9.25 7.10 0.45 0.20 0.75 Note 2 Note 2 NOTE A2 A Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 32A REV. B R 117 1042H-AVR-04/03 28P3 D PIN 1 E1 A SEATING PLANE L B1 e E B B2 A1 (4 PLACES) C eB 0 ~ 15 REF SYMBOL A A1 D E E1 B COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.508 34.544 7.620 7.112 0.381 1.143 0.762 3.175 0.203 - NOM - - - - - - - - - - - MAX 4.5724 - 34.798 8.255 7.493 0.533 1.397 1.143 3.429 0.356 10.160 Note 1 Note 1 NOTE Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 B2 L C eB e 2.540 TYP 09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 28P3 REV. B R 118 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Errata for AT90S/LS4433 Rev. Rev. C/D/E/F * * * * * * * BOD Keeps the Device in Reset at Low Temperature Fuses and Programming Mode Incorrect Channel Change in Free Running Mode Bandgap Reference Stabilizing Time Brown-out Detection Level Serial Programming at Voltages below 2.9V UART Loses Synchronization if RXD Line is Low when UART Receive is Disabled 7. BOD Keeps the Device in Reset at Low Temperature When the device operates at low temperature (below 0C) and the BOD is enabled, tha part may fail to start up. AT low temperature the BOD may never release the reset, and the part will not start the application. The problem will only occur during start-up and an already running application wil not go into reset even if the temperature goes below 0C. Note that this also affects the described workaround for Errata no. 4. Problem Fix/Workaround If the device operates at low temperature and a BOD is required, an external BOD c i r c u i t m u s t b e u s e d . A l t e r n a t i v e l y , A T m e g a 8 c a n b e u s e d i n s te a d o f AT90S/LS4433. 6. Fuses and Programming Mode After programming the Fuses in Serial Programming mode, it is not possible to program the Flash or EEPROM. If leaving Programming mode, it is not possible to reenter Programming mode. Problem Fix/Workaround Power the part down and backup again after programming the Fuses or leaving Programming mode. 5. Incorrect Channel Change in Free Running Mode If the ADC operates in Free Running mode and channels are changed by writing to ADMUX, shortly after the ADC Interrupt Flag (ADIF in ADCSR) is set, the new setting in ADMUX may affect the ongoing conversion. Problem Fix/Workaround Use Single Conversion mode when scanning channels, or avoid changing ADMUX util at least 0.5 ADC clock cycles after ADIF goes high. 4. Bandgap Reference Stabilizing Time The time for the internal voltage reference for the Analog Comparator to stabilize is longer than specified. The stabilizing period starts after the bandgap reference has been selected, and can go on for as much as 10 seconds. Problem Fix/Workaround The Bandgap reference will be stable immediately if the internal Brown-out Detector is enabled. 119 1042H-AVR-04/03 3. Brown-out Detection Level The Brown-out Detection level can increase when there is heavy I/O-activity on the device. The increase can be significant when some of the I/O pins are driving heavy loads. Problem Fix/Workaround Select a VCC well above the Brown-out Detection level. Avoid loading I/O ports with high capacitive or resistive loads. 2. Serial Programming at Voltages below 2.9V At voltages below 2.9V, serial programming might fail. Problem Fix/Workaround Keep VCC at 2.9V or higher during In-System Programming. 1. UART Loses Synchronization if RXD Line is Low when UART Receive is Disabled The UART will detect a UART start bit and start reception even if the UART is not enabled. If this occurs, the first byte after reenabling the UART will be corrupted. Problem Fix/Workaround Make sure that the RX line is high at start-up and when the UART is disabled. An external RS-232 level converter keeps the line high during start-up. 120 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Data Sheet Change Log for AT90S/LS4433 Changes from Rev. 1042E-09/01 to Ref. 1042F-03/02 This section containes a log on the changes made to the data sheet for AT90S/LS4433. All refereces to pages in Change Log, are referred to this document. 1 2 3 Updated minimum AREF Voltage on page 5 and page 64. Corrected VBOT Max for BODLEVEL = 1 in Table 4 on page 22. Updated Corporate Template. Added wathermark "Not recommended for new designs. Use ATmega8". Added Errata Sheet to the Data Sheet. Updated the "Errata for AT90S/LS4433 Rev. Rev. C/D/E/F" on page 119. Updated "Packaging Information" on page 117. Changes from Rev. 1042F-03/02 to Ref. 1042G-09/02 Changes from Rev. 1042G-09/02 to Ref. 1042H-04/03 1 2 1 2 121 1042H-AVR-04/03 122 AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Table of Contents Features................................................................................................. 1 Pin Configurations................................................................................ 2 Description ............................................................................................ 3 Block Diagram ...................................................................................................... 4 Pin Descriptions.................................................................................................... 5 Clock Options ....................................................................................................... 6 Architectural Overview......................................................................... 7 General Purpose Register File ........................................................................... ALU - Arithmetic Logic Unit................................................................................ In-System Programmable Flash Program Memory ............................................ SRAM Data Memory........................................................................................... Program and Data Addressing Modes................................................................ EEPROM Data Memory...................................................................................... Memory Access Times and Instruction Execution Timing .................................. I/O Memory ......................................................................................................... Reset and Interrupt Handling.............................................................................. Sleep Modes....................................................................................................... 10 11 11 11 12 16 16 17 20 31 Timer/Counters ................................................................................... 33 Timer/Counter Prescaler..................................................................................... 33 8-bit Timer/Counter0........................................................................................... 33 16-bit Timer/Counter1......................................................................... 35 Watchdog Timer.................................................................................. 43 EEPROM Read/Write Access............................................................. 45 Prevent EEPROM Corruption ............................................................................. 47 Serial Peripheral Interface - SPI........................................................ 48 SS Pin Functionality............................................................................................ 49 Data Modes ........................................................................................................ 50 UART.................................................................................................... 53 Data Transmission.............................................................................................. 53 Data Reception ................................................................................................... 54 UART Control ..................................................................................................... 57 Analog Comparator ............................................................................ 62 i 1042H-AVR-04/03 Analog-to-Digital Converter............................................................... 64 Features.............................................................................................................. Operation ............................................................................................................ Prescaling ........................................................................................................... ADC Noise Canceler Function............................................................................ Scanning Multiple Channels ............................................................................... ADC Noise Canceling Techniques ..................................................................... ADC Characteristics TA = -40C to 85C ............................................................ 64 65 65 67 70 70 71 I/O Ports............................................................................................... 72 Port B.................................................................................................................. 72 Port C.................................................................................................................. 77 Port D.................................................................................................................. 80 Memory Programming........................................................................ 85 Program and Data Memory Lock Bits................................................................. Fuse Bits............................................................................................................. Signature Bytes .................................................................................................. Programming the Flash and EEPROM............................................................... Parallel Programming ......................................................................................... Parallel Programming Characteristics ................................................................ Serial Downloading............................................................................................. Serial Programming Characteristics ................................................................... 85 85 85 86 86 92 93 97 Electrical Characteristics................................................................... 98 Absolute Maximum Ratings*............................................................................... 98 DC Characteristics.............................................................................................. 98 External Clock Drive Waveforms .................................................... 100 Typical Characteristics .................................................................... 101 Register Summary ............................................................................ 112 Instruction Set Summary ................................................................. 114 Ordering Information........................................................................ 116 Packaging Information ..................................................................... 117 32A ................................................................................................................... 117 28P3 ................................................................................................................. 118 Errata for AT90S/LS4433 Rev. Rev. C/D/E/F................................... 119 ii AT90S/LS4433 1042H-AVR-04/03 AT90S/LS4433 Data Sheet Change Log for AT90S/LS4433.................................... 121 Changes from Rev. 1042E-09/01 to Ref. 1042F-03/02 .................................... 121 Changes from Rev. 1042F-03/02 to Ref. 1042G-09/02.................................... 121 Changes from Rev. 1042G-09/02 to Ref. 1042H-04/03 ................................... 121 Table of Contents .................................................................................. i iii 1042H-AVR-04/03 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) and AVR(R) are the registered trademarks of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 1042H-AVR-04/03 0M |
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